参数资料
型号: MAX6852AEE+T
厂商: Maxim Integrated
文件页数: 19/32页
文件大小: 0K
描述: IC VFD CTRLR MATRIX 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: 真空荧光 (VF)
配置: 5 x 7(矩阵)
接口: 串行
电流 - 电源: 3.5mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
4-Wire Interfaced, 5 ? 7 Matrix Vacuum-
Fluorescent Display Controller
1-1
2-1
3-1
4-1
5-1
100 μ s MULTIPLEX TIME PERIOD (OSC = 4MHz)
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
(A)
(C)
(D)
(E)
(B)
1-2
SEG 6
1-3
SEG 11
2-2
SEG 7
2-3
SEG 12
3-2
SEG 8
3-3
SEG 13
4-2
SEG 9
4-3
SEG 14
5-2
SEG 10
5-3
SEG 15
PHASE 1
PHASE 2
Figure 13. Filament Bridge Driver Timing Waveforms
1-4
SEG 16
2-4
SEG 17
3-4
SEG 18
4-4
SEG 19
5-4
SEG 20
1-5
2-5
3-5
4-5
5-5
VFIL
SEG 21
SEG 22
SEG 23
SEG 24
SEG 25
R2
Q2
Q4
R4
1-6
2-6
3-6
4-6
5-6
SEG 26
1-7
SEG 31
SEG 27
2-7
SEG 32
SEG 28
3-7
SEG 33
SEG 29
4-7
SEG 34
SEG 30
5-7
SEG 35
PHASE 1
VFD TUBE
CURSOR
PHASE 2
Q1
Q3
Figure 12. Relationship Between Segment Output and VFD
Tube 5 ? 7 Matrix Dots
GND
GND
Figure 14. Filament Bridge Driver (MOSFET)
Figure 14 shows the external components required for
the filament driver using a FET bridge.
PHASE1 and PHASE2 Outputs
PHASE1 and PHASE2 can be individually programmed
as one of four output types (Tables 36, 37).
When using the filament drive, first ensure that the fila-
ment duty-cycle register 0x09 is set to the correct value
before configuring the PHASE1 and PHASE2 outputs to
be filament drives. To stop the filament drive, program
either PHASE1 or PHASE2 (or both) to be logic-low gen-
eral-purpose outputs. Both PHASE1 and PHASE2 out-
puts come out of power-on-reset in logic-low condition.
PUMP Output
The PUMP output can be programmed as one of four
output types (Table 38).
PORT0 and PORT1 Outputs
PORT0 and PORT1 can be individually programmed as
one of eight output types (Tables 39, 40). The PORT1
choices are similar to the PORT0 choices, except that
the last four items are invert logic. PORT0 output comes
out of power-on-reset in logic-low condition, whereas
PORT1 output initializes high.
The PORT0 and PORT1 shutdown outputs allow exter-
nal hardware (for example, a DC-DC converter power
supply for VFD) to be disabled by the MAX6852 when
the MAX6852 is shut down.
The 625Hz, 1250Hz, and 2500Hz outputs can drive a
piezo sounder either from PORT0 or PORT1 alone, or
by both ports together as bridge drive. For bridge
drive, the sounder is connected between PORT0 and
PORT1, taking advantage of the PORT1 output being
inverted with respect to PORT0. Select different fre-
quencies for PORT0 and PORT1 to obtain a wider
range of sounds when bridge drive is used.
Multiplex Clock and Blink Timing
The OSC1 and OSC2 inputs set the multiplex and blink
timing for the display driver. Connect an external resis-
tor from OSC2 to GND and an external capacitor C OSC
from OSC1 to GND to set the frequency of the internal
RC oscillator. Alternatively, overdrive OSC1 with an
external TTL or CMOS clock. If an exact blink rate or
multiplex period is required, use an external clock
ranging between 2MHz and 8MHz to drive OSC1.
______________________________________________________________________________________
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