参数资料
型号: MAX6852AEE+T
厂商: Maxim Integrated
文件页数: 14/32页
文件大小: 0K
描述: IC VFD CTRLR MATRIX 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: 真空荧光 (VF)
配置: 5 x 7(矩阵)
接口: 串行
电流 - 电源: 3.5mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
4-Wire Interfaced, 5 ? 7 Matrix Vacuum-
Fluorescent Display Controller
CS
t CSW
t CSS
t CL
t CH
t CP
t CSH
SCLK
t DS
t DH
DIN
DN
DN-1
D1
D0
t CSU
DOUT
Figure 6. 4-Wire Serial Interface Timing Diagram
CS
CLK
D15
=0
D15
DIN
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
Figure 7. 16-Bit Write Transmission to the MAX6852
If fewer or greater than 16 bits are clocked into the
MAX6852 between taking CS low and taking CS high
again, the MAX6852 stores the last 16 bits received,
including the previous transmission(s). The general
case is when n bits (where n > 16) are transmitted to
the MAX6852. The last bits comprising bits {n-15} to {n}
are retained and are parallel loaded into the 16-bit latch
as bits D15 to D0, respectively (Figure 8).
Reading Device Registers
Any register data within the MAX6852 may be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is high,
indicating a read command, and bits D14 through
D15 = 0
D8 contain the address of the register to read. Bits
D7 to D0 contain dummy data, which is discarded.
4) Take CS high. Positions D7 through D0 in the shift
register are now loaded with the data in the register
addressed by bits D15 through D8.
5) Take SCLK low.
6) Issue another read or write command (which can be
no-op), and examine the bit stream at DOUT; the
first 8 bits contain the address of the register that
was read ( Note: The MSB, which was transmitted as
a 1 for a read command, may read back either as a
1 or a zero). The second 8 bits are the contents of
the register addressed by bits D14 through D8 in
Step 3.
VFD Driver Serial Interface
The VFD driver interface on the MAX6852 is a serial
interface using three output pins, VFLOAD, VFCLK, and
VFDOUT (Figure 9) to drive industry-standard, shift-reg-
14
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