参数资料
型号: MAX6852AEE+T
厂商: Maxim Integrated
文件页数: 5/32页
文件大小: 0K
描述: IC VFD CTRLR MATRIX 16QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: 真空荧光 (VF)
配置: 5 x 7(矩阵)
接口: 串行
电流 - 电源: 3.5mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
4-Wire Interfaced, 5 ? 7 Matrix Vacuum-
Fluorescent Display Controller
Typical Operating Characteristics (continued)
(Typical operating circuit, V+ = 3.3V, T A = +25 ° C, unless otherwise noted.)
DEAD-CLOCK OSC FREQUENCY
2.5
f OSC vs. TEMPERATURE
V+ = 2.7V
0.18
0.16
vs. TEMPERATURE
2.0
1.5
V+ = 3.3V
V+ = 3.6V
0.14
0.12
0.10
V+ = 3.6V
1.0
0.08
V+ = 3.3V
0.06
V+ = 2.7V
0.5
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE ( ° C)
0.04
0.02
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE ( ° C)
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NAME
VFCLK
VFDOUT
VFLOAD
VFBLANK
PUMP
PHASE1
PHASE2
V+
GND
PORT0
SCLK
DIN
CS
PORT1
FUNCTION
Serial-Clock Output to External Driver. Push-pull clock output to external display driver. On VFCLK ’ s
falling edge, data is clocked out of VFDOUT.
Serial-Data Output to External Driver. Push-pull data output to external display driver.
Serial-Load Output to External Driver. Push-pull load output to external display driver. Rising edge is
used by external display driver to load serial data into display latch.
Display Blanking Output to External Driver. Push-pull blanking output to external display driver used for
PWM intensity control.
Charge-Pump Output and General-Purpose Output. User-configurable push-pull logic output can also
be used as a driver for external charge pump.
Filament Drive PHASE1 Output and General-Purpose Output. User-configurable push-pull logic output
can also be used as a driver for external filament bridge drive.
Filament Drive PHASE2 Output and General-Purpose Output. User-configurable push-pull logic output
can also be used as a driver for external filament bridge drive.
Positive Supply Voltage. Bypass V+ to GND with a 0.1μF ceramic capacitor.
Ground
PORT0 General-Purpose Output. User-configurable push-pull logic output.
Serial-Clock Input. On SCLK ’ s rising edge, data shifts into the internal shift register, and data is
clocked out of DOUT. SCLK is active only while CS is low.
Serial-Data Input. Data from DIN loads into the internal 16-bit shift register on SCLK ’ s rising edge.
Chip-Select Input. Serial data is loaded into the shift register while CS is low. The most recent 16 bits of
data latch on CS ’ s rising edge.
PORT1 General-Purpose Output. User-configurable push-pull logic output.
_______________________________________________________________________________________
5
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