参数资料
型号: MAX7032ATJ+T
厂商: Maxim Integrated
文件页数: 18/32页
文件大小: 0K
描述: IC TRASCEIVER ASK/FSK 32TQFN
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 300MHz ~ 450MHz
数据传输率 - 最大: 33kbps
调制或协议: ASK,FSK,OOK
应用: 车库门开启器,遥控,双向 RKE
功率 - 输出: 10dBm
灵敏度: -114dBm
电源电压: 2.1 V ~ 3.6 V,4.5 V ~ 5.5 V
电流 - 接收: 6.7mA
电流 - 传输: 12.5mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 125°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Crystal Oscillator (XTAL)
The XTAL oscillator in the MAX7032 is designed to pre-
sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2 pins. In most cases, this corre-
sponds to a 4.5pF load capacitance applied to the
external crystal when typical PCB parasitics are added.
It is very important to use a crystal with a load
capacitance that is equal to the capacitance of the
MAX7032 crystal oscillator plus PCB parasitics. If a
crystal designed to oscillate with a different load
capacitance is used, the crystal is pulled away from its
stated operating frequency, introducing an error in the
reference frequency. Crystals designed to operate with
higher differential load capacitance always pull the ref-
erence frequency higher.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
f p is the amount the crystal frequency is pulled in ppm.
C m is the motional capacitance of the crystal.
C CASE is the case capacitance.
C SPEC is the specified load capacitance.
C LOAD is the actual load capacitance.
When the crystal is loaded as specified, i.e., C LOAD =
C SPEC , the frequency pulling equals zero.
Serial Control Interface
Communication Protocol
The MAX7032 programs through a 3-wire interface. The
data input must follow the timing diagrams shown in
Figures 7, 8, and 9.
Note that the DIO line must be held LOW while CS is
high. This is to prevent the MAX7032 from entering dis-
continuous receive mode if the DRX bit is high. The
data is latched on the rising edge of SCLK, and there-
fore must be stable before that edge. The data
sequencing is MSB first, the command (C[1:0] see
Table 2), the register address (A[5:0] see Table 3), and
the data (D[7:0] see Table 4).
C m ? 1 1 ?
? C
C CASE + C SPEC ? ?
f P =
2 ? CASE + C LOAD
?
× 10 6
Table 2. Command Bits
C[1:0]
0x0
DESCRIPTION
No operation
CS
t CS
0x1
0x2
0x3
Write data
Read data
Master reset
SCLK
t SC
t CSS
t CL
t CH
t CSH
t DS
t DH
t TH
t DV
t DO
t TR
DIO
HI-Z
HI-Z
D7
D0
HI-Z
DATA IN
Figure 7. Serial Interface Timing Diagram
DATA OUT
18
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