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参数资料
| 型号： | MAX7032ATJ+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 19/32页 |
| 文件大小： | 0K |
| 描述： | IC TRASCEIVER ASK/FSK 32TQFN |
| 其它有关文件： | Automotive Product Guide |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 频率： | 300MHz ~ 450MHz |
| 数据传输率 - 最大： | 33kbps |
| 调制或协议： | ASK，FSK，OOK |
| 应用： | 车库门开启器，遥控，双向 RKE |
| 功率 - 输出： | 10dBm |
| 灵敏度： | -114dBm |
| 电源电压： | 2.1 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 电流 - 接收： | 6.7mA |
| 电流 - 传输： | 12.5mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Table 3. Register Summary
REGISTER A[5:0]
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x1A
REGISTER NAME
Power configuration
Control
Configuration0
Configuration1
Oscillator frequency
Off timer—t OFF (upper byte)
Off timer—t OFF (lower byte)
CPU recovery timer—t CPU
RF settling timer—t RF (upper
byte)
RF settling timer—t RF (lower
byte)
On timer—t ON (upper byte)
On timer—t ON (lower byte)
Transmitter low-frequency
setting—TxLOW (upper byte)
Transmitter low-frequency
setting—TxLOW (lower byte)
Transmitter high-frequency
setting—TxHIGH (upper byte)
Transmitter high-frequency
setting—TxHIGH (lower byte)
Status register (read only)
DESCRIPTION
Enables/disables the LNA, AGC, mixer, baseband, peak
detectors, PA, and RSSI output (see Table 5).
Controls AGC lock, gain state, peak-detector tracking, polling
timer and FSK calibration, clock signal output, and sleep mode
(see Table 6).
Sets options for modulation, TX/RX mode, manual-gain mode,
discontinuous receive mode, off-timer and on-timer prescalers
(see Table 7).
Sets options for automatic FSK calibration, clock output, output
clock divider ratio, AGC dwell timer (see Tables 8, 10, 11, and 12).
Sets the internal clock frequency divisor. This register must be set
to the integer result of f XTAL /100kHz (see the Oscillator Frequency
Register (Address 0x05) section).
Sets the duration that the MAX7032 remains in low-power mode
when DRX is active (see Table 12).
Increases maximum time the MAX7032 stays in lower power mode
while CPU wakes up when DRX is active (see Table 13).
During the time set by the RF settling timer, the MAX7032 is
powered on with the peak detectors and the data outputs disabled
to allow time for the RF section to settle. DIO must be driven low at
any time during t LOW = t CPU + t RF + t ON or the timer sequence
restarts (see Table 14).
Sets the duration that the MAX7032 remains in active mode when
DRX is active (see Table 15).
Sets the low frequency (FSK) of the transmitter or the carrier
frequency of ASK for the fractional-N synthesizer.
Sets the high frequency (FSK) of the transmitter for the fractional-N
synthesizer.
Provides status for PLL lock, AGC state, crystal operation, polling
timer, and FSK calibration (see Table 9).
______________________________________________________________________________________
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