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参数资料
| 型号： | MAX7032ATJ+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 24/32页 |
| 文件大小： | 0K |
| 描述： | IC TRASCEIVER ASK/FSK 32TQFN |
| 其它有关文件： | Automotive Product Guide |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 频率： | 300MHz ~ 450MHz |
| 数据传输率 - 最大： | 33kbps |
| 调制或协议： | ASK，FSK，OOK |
| 应用： | 车库门开启器，遥控，双向 RKE |
| 功率 - 输出： | 10dBm |
| 灵敏度： | -114dBm |
| 电源电压： | 2.1 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 电流 - 接收： | 6.7mA |
| 电流 - 传输： | 12.5mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Table 9. Status Register (Read Only) (Address: 0x1A)
BIT ID
BIT NAME
BIT LOCATION
(0 = LSB)
FUNCTION
1 = Internal PLL is locked
LCKD
Lock detect
7
0 = Internal PLL is not locked so the
MAX7032 does not receive or transmit data
GAINS
AGC gain state
6
1 = LNA in high-gain state
0 = LNA in low-gain state
1 = Valid clock at crystal inputs
CLKON
Clock/crystal alive
5
0 = No valid clock signal seen at the crystal
inputs
X
X
X
PCALD
None
None
None
Polling timer calibration
done
4
3
2
1
Zero
Zero
Zero
1 = Polling timer calibration is completed
0 = Polling timer calibration is in progress or
not completed
1 = FSK calibration is completed
FCALD
FSK calibration done
0
0 = FSK calibration is in progress or not
completed
Table 10. Clock Output Divider Ratio
Configuration
hexadecimal value written to the oscillator frequency
register is the nearest integer result of f XTAL /100kHz.
For example, if data is being received at 315MHz, the
CKOUT
0
1
1
1
1
CDIV1
X
0
0
1
1
CDIV0
X
0
1
0
1
CLOCKOUT
FREQUENCY
Disabled at logic 0
f XTAL
f XTAL /2
f XTAL /4
f XTAL /8
crystal frequency is 12.67917MHz. Dividing the crystal
frequency by 100kHz and rounding to the nearest inte-
ger gives 127, or 0x7F hex. So for 315MHz, 0x7F would
be written to the oscillator frequency register.
AGC Dwell Timer (Address 0x03)
The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
Oscillator Frequency Register (Address 0x05)
The MAX7032 has an internal frequency divider that
divides down the crystal frequency to 100kHz. The
MAX7032 uses the 100kHz clock signal when calibrat-
ing itself and also to set image-rejection frequency. The
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and a low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.
24
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