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参数资料
| 型号： | MAX7032ATJ+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 26/32页 |
| 文件大小： | 0K |
| 描述： | IC TRASCEIVER ASK/FSK 32TQFN |
| 其它有关文件： | Automotive Product Guide |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 频率： | 300MHz ~ 450MHz |
| 数据传输率 - 最大： | 33kbps |
| 调制或协议： | ASK，FSK，OOK |
| 应用： | 车库门开启器，遥控，双向 RKE |
| 功率 - 输出： | 10dBm |
| 灵敏度： | -114dBm |
| 电源电压： | 2.1 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 电流 - 接收： | 6.7mA |
| 电流 - 传输： | 12.5mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
CS
DIO
t OFF
t CPU
t OFF
t CPU
t LOW
t RF
t ON
ASK_DATA OR
FSK_DATA
Figure 10. DRX Mode Sequence of the MAX7032
Set OFPS1 to be 1 and OFPS0 to be 1. That sets the
t OFF time base (1 LSB) to be 7680μs. Set REG 0x06
and REG 0x07 to be FFFF, which is 65535 in decimal.
Therefore, the total t OFF is:
t OFF = 7680μs x 65535 = 8min 23s
During t OFF , the MAX7032 is operating with very low
supply current (23.4μA typ), where all its modules are
turned off, except for the t OFF timer itself. Upon com-
pletion of the t OFF time, the MAX7032 signals the user
by asserting DIO low.
CPU Recovery Timer (t CPU )
The CPU recovery timer, t CPU (see Figure 10), is used
to delay power up of the MAX7032, thereby providing
extra power savings and giving the CPU time to com-
plete its own power-on sequence. The CPU is signaled
to begin powering up when the DIO line is pulled low
by the MAX7032 at the end of t OFF . Then, t CPU begins
counting, while DIO is held low by the MAX7032. At the
t RF
t ON
RF Settling Timer (t RF )
The RF settling timer, t RF (see Figure 10), allows the RF
sections of the MAX7032 to power up and stabilize
before ASK or FSK data is received. t RF begins count-
ing once t CPU has expired. At the beginning of t RF , the
modules selected in the power control register (register
0x00) are all powered up and the peak detectors are in
the track mode and have the t RF period to settle.
t RF is a 16-bit timer, configured through register 0x09
(upper byte) and register 0x0A (lower byte). The possi-
ble t RF settings are listed in Table 14. The data written
to the t RF register (register 0x09 and register 0x0A) are
multiplied by 120μs to give the total t RF time. See the
example in the CPU Recovery Timer (t CPU ) section. On
power-up, the RF timer registers are reset to zero and
must be written before using DRX mode.
Table 13. CPU Recovery Timer (t CPU )
Configuration
end of t CPU , the t RF counter begins.
t CPU is an 8-bit timer, configured through register 0x08.
The possible t CPU settings are summarized in Table 13.
The data written to the t CPU register (register 0x08) is
multiplied by 120μs to give the total t CPU time. See the
TIME BASE
(μs)
120
MIN t CPU
REG 0x08 = 0x01
(μs)
120
MAX t CPU
REG 0x08 = 0xFF
(ms)
30.6
example below. On power-up, the CPU timer register is
reset to zero and must be written before using DRX
mode.
Table 14. RF Settling Timer (t RF )
Configuration
Set REG 0x08 to be FF in hex, which is 255 in decimal.
Therefore, the total t CPU is:
t CPU = 120μs x 255 = 30.6ms
t RF TIME BASE
(μs)
120
MIN t RF
REG 0x09 = 0x00
REG 0x0A = 0x01
(μs)
120
MAX t RF
REG 0x09 = 0xFF
REG 0x0A = 0xFF
(s)
7.86
26
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