参数资料
型号: MAX97003EWP+T
厂商: Maxim Integrated Products
文件页数: 21/48页
文件大小: 0K
描述: IC AUDIO SUBSYSTEM LN 20WLP
标准包装: 2,500
类型: D 类;H 类
输出类型: 1-通道(单声道)或 2-通道(立体声)
在某负载时最大输出功率 x 通道数量: 1W x 2 @ 8 欧姆
电源电压: 2.7 V ~ 5.5 V
特点: 消除爆音,差分输入,关闭
安装类型: *
供应商设备封装: *
封装/外壳: *
包装: *
Maxim Integrated Products 28
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Class H Operation
A Class H amplifier uses a Class AB output stage with
power supplies that are modulated by the output signal.
In the case of the IC, two nominal power-supply differen-
tials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V)
are available from the charge pump. Figure 14 shows the
operation of the output voltage dependent power supply.
Ground Sense
The headphone amplifier features output ground sensing
that is used to reduce ground loop noise when the head-
phone output jack is connected to a different ground than
the amplifier ground. An example of this is when the head-
phone jack is used as a lineout and connected to an exter-
nal power amplifier. In addition, the ground sense reduces
noise that can be caused by voltage drops between the
amplifier ground and the headphone jack ground pin dur-
ing normal headphone use. HPSNS must be connected to
the ground pin on the headphone jack.
Volume-Change Features
The IC includes several features that enhance perfor-
mance during volume changes. Zero-crossing detec-
tion, volume slewing, and enhanced volume smoothing
are used to improve click-and-pop performance during
volume changes. Volume readback is used to report the
actual volume setting after the DRC, expander, or distor-
tion limiter applies an automatic volume change.
Zero-Crossing Detection
The IC features zero-crossing detection to reduce clicks
and pops during volume changes. When zero-crossing
detection is enabled, all volume changes are delayed
until a zero-crossing has been detected. If no zero-cross-
ing is detected within 100ms, then the zero-crossing
detector times out and volume changes are executed.
Disabling zero-crossing detection allows volume chang-
es to occur immediately.
Volume Slewing
The IC offers volume slewing for all volume changes
to further reduce clicks and pops. When enabled, the
IC ramps through intermediate volume settings when a
change to the volume is made. If zero-crossing detection
is disabled, slewing occurs at a rate of 0.2ms per step.
If zero-crossing detection is enabled, slew time depends
on the input signal. If the duration between zero-cross-
ings is less than 0.2ms, the slew time is limited at 0.2ms
per volume change. If the duration between zero-cross-
ings is longer than 0.2ms, volume changes occur at each
zero-crossing. Volume slewing also provides a soft-start
at power-on and soft-stop at power-off.
Enhanced Volume Smoothing
Enhanced volume smoothing can be used when the vol-
ume slewing feature is enabled. When enhanced volume
smoothing is enabled and a volume change occurs, the
IC waits for each step in the ramp to be applied before
executing the next step. When zero-crossing detection
is enabled, enhanced volume smoothing prevents large
steps in the output volume when no zero-crossings are
detected.
Volume Readback
The IC features three volume readback registers that
report the actual volume settings of the speaker, left
headphone, and right headphone volume registers. The
DRC, expander, and distortion limiter are capable of
automatically adjusting these volume registers according
to their respective settings.
I2C Slave Address
The IC’s audio subsystem uses a slave address of 0x9A
or 1001101 R/W. The address is defined as the 7 most
significant bits (MSBs) followed by the read/write bit. Set
the read/write bit to 1 to configure the audio subsystem to
read mode. Set the read/write bit to 0 to configure the IC
to write mode. The address is the first byte of information
sent to the IC after the START condition.
Registers Map
19 internal registers program the audio subsystem.
Table 1 lists all of the registers, their addresses, and
power-on-reset states. Register 0xFF indicates the
device revision. Write zeros to all unused bits in the
register table when updating the register, unless other-
wise noted.
Figure 14. Class H Operation
32ms
1.8V
0.9V
VTH
-0.9V
-1.8V
HPVDD
HPVSS
OUTPUT
VOLTAGE
32ms
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