参数资料
型号: MAX97003EWP+T
厂商: Maxim Integrated Products
文件页数: 35/48页
文件大小: 0K
描述: IC AUDIO SUBSYSTEM LN 20WLP
标准包装: 2,500
类型: D 类;H 类
输出类型: 1-通道(单声道)或 2-通道(立体声)
在某负载时最大输出功率 x 通道数量: 1W x 2 @ 8 欧姆
电源电压: 2.7 V ~ 5.5 V
特点: 消除爆音,差分输入,关闭
安装类型: *
供应商设备封装: *
封装/外壳: *
包装: *
Maxim Integrated Products 40
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
Table 12. Power Management Register
Power Management
The power management register allows the speaker, left headphone, and right headphone signal paths to be enabled.
It also enables the IC device.
I2C Serial Interface
The IC features an I2C/SMBus-compatible, two-wire seri-
al interface consisting of a serial-data line (SDA) and a
serial-clock line (SCL). SDA and SCL facilitate communi-
cation between the IC and the master at clock rates up to
400kHz. Figure 1 shows the two-wire interface timing dia-
gram. The master generates SCL and initiates data trans-
fer on the bus. The master device writes data to the IC
by transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START (S) or REPEATED
START (Sr) condition, a not acknowledge, and a STOP
Figure 15. I2C Serial Interface Timing Diagram
REGISTER
BIT
NAME
DESCRIPTION
0x12
7
SHDN
Software Shutdown
0 = Device disabled
1 = Device enabled
2
SPKEN
Speaker Amplifier Enable
0 = Disabled
1 = Enabled
1
HPLEN
Left Headphone Amplifier Enable
0 = Disabled
1 = Enabled
0
HPREN
Right Headphone Amplifier Enable
0 = Disabled
1 = Enabled
SCL
SDA
tR
tF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT
tLOW
tHIGH
tHD,STA
tSP
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