参数资料
型号: MAX97003EWP+T
厂商: Maxim Integrated Products
文件页数: 36/48页
文件大小: 0K
描述: IC AUDIO SUBSYSTEM LN 20WLP
标准包装: 2,500
类型: D 类;H 类
输出类型: 1-通道(单声道)或 2-通道(立体声)
在某负载时最大输出功率 x 通道数量: 1W x 2 @ 8 欧姆
电源电压: 2.7 V ~ 5.5 V
特点: 消除爆音,差分输入,关闭
安装类型: *
供应商设备封装: *
封装/外壳: *
包装: *
Maxim Integrated Products 41
MAX97003
High-Efficiency, Low-Noise Audio Subsystem
(P) condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500I, is required on SDA. SCL operates only as an
input. A pullup resistor, typically greater than 500I, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the IC from
high voltage spikes on the bus lines, and minimize cross-
talk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high are
control signals. See the START and STOP Conditions
section.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition on
SDA while SCL is high (Figure 16). A START condition
from the master signals the beginning of a transmission
to the IC. The master terminates transmission, and frees
the bus, by issuing a STOP condition. The bus remains
active if a REPEATED START condition is generated
instead of a STOP condition.
Early STOP Conditions
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the same
SCL high pulse as the START condition.
Slave Address
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
IC, the seven most significant bits are 1001101. Setting
the read/write bit to 1 (slave address = 0x9B) configures
the IC for read mode. Setting the read/write bit to 0 (slave
address = 0x9A) configures the IC for write mode. The
address is the first byte of information sent to the IC after
the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked ninth bit that the
IC uses to handshake receipt each byte of data when
in write mode (Figure 17). The IC pulls down SDA dur-
ing the entire master-generated ninth clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master retries com-
munication. The master pulls down SDA during the ninth
clock cycle to acknowledge receipt of data when the IC
is in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue. A
not-acknowledge is sent when the master reads the final
byte of data from the IC, followed by a STOP condition.
Figure 16. START, STOP, and REPEATED START Conditions
Figure 17. Acknowledge
SCL
SDA
SSrP
1
SCL
START
CONDITION
SDA
28
9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
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