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参数资料
| 型号： | MB85317A-60 |
| 厂商： | Fujitsu Limited |
| 英文描述： | CMOS 4M×72Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 4M×72位 同步动态RAM) |
| 中文描述： | 4米× 72Bit的CMOS同步动态随机存取存储器（SDRAM）的CMOS（4分× 72位同步动态RAM）的 |
| 文件页数： | 11/13页 |
| 文件大小： | 201K |
| 代理商： | MB85317A-60 |
11
MB85317A-60/MB85317A-70
Notes: 1.
An initial pause (RAS=CAS=V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-only
cycles before proper device operation is achieved. If an internal refresh counter is used, a minimum of
eight CAS-before-RAS initialization cycles are required instead of eight RAS cycles.
AC characteristics assume t
T
= 5ns.
V
IH
(min.) and V
IL
(max.) are reference levels for measureing the timing of input signals. Transition times
are measured between V
IH
(min.) and V
IL
(max.).
Assumes that t
RCD
≤
t
RCD
(max.), t
RAD
≤
t
RAD
(max.). If t
RCD
is greater than the maximum recommended
value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown.
If t
RCD
≥
t
RCD
(max.), t
RAD
≥
t
RAD
(max.), and t
ASC
≥
t
AA
– t
CAC
– t
T
, access time is t
CAC
.
If t
RAD
≥
t
RAD
(max.) and t
ASC
≤
t
AA
– t
CAC
– t
T
, access time is t
AA
.
Measured with a load equivalent to two TTL loads and 100 pF.
t
OFF
is specified that output buffer change to high impedance state.
Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as
a reference point only; if t
RCD
is greater than the specified t
RCD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
10. t
RCD
(min.) = t
RAH
(min.)+ 2t
T
+ t
ASC
(min.).
11. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as
a reference point only; if t
RAD
is greater than the specified t
RAD
(max.) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
12. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
13. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min.) the data output pin will remain High-Z
state through entire cycle.
14. Assumes that t
WCS
< t
WCS
(min.).
15. Either t
DZC
or t
DZO
must be satisfied.
16. t
CPA
is access time from the selection of a new column address (caused by changing CAS from “L” to
“H”). Therefore, if t
CP
become long, t
CPA
also become longer than t
CPA
(max.).
17. Assumes that CAS-before-RAS refresh.
18. t
WCS
, t
CWD
, t
RWD
, t
AWD
, and t
CPWD
are not restrictive operating parameters. They are included in the data
sheet as an electrical characteristic only. If t
WCS
≥
t
WCS
(min.), the cycle is an early write cycle and Dout
pin will maintain high impedance state thoughout the entire cycle. If t
CWD
≥
t
CWD
(min.), t
RWD
≥
t
RWD
(min.), t
AWD
≥
t
AWD
(min.), and t
CPWD
≥
t
CPWD
(min.), the cycle is a read-modify-write cycle and data from
the selected cell will appear at the Dout pin. If neither of the above conditions is satisfied, the cycle is
a delayed write cycle and invalid data will appear the Dout pin, and write operation can be executed
by satisfying t
RWL
, t
CWL
, t
RAL
and t
CAL
specifications.
*Source: See MB8116400A Data Sheet for details on the electricals.
2.
3.
4.
5.
6.
7.
8.
9.
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