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参数资料
| 型号： | MB9AF311MPMC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80 |
| 封装： | 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 98/114页 |
| 文件大小： | 1357K |
| 代理商： | MB9AF311MPMC |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
84
15.5
Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the output compare registers (OCR0A and OCR0B). Whenever
TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the output compare flag (OCF0A or
OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output
compare interrupt. The output compare flag is automatically cleared when the interrupt is executed. Alternatively, the flag
can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to
generate an output according to operating mode set by the WGM02:0 bits and compare output mode (COM0x1:0) bits. The
max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some
modes of operation (Section 15.7 “Modes of Operation” on page 86).
Figure 15-3 shows a block diagram of the output compare unit.
Figure 15-3. Output Compare Unit, Block Diagram
The OCR0x registers are double buffered when using any of the pulse width modulation (PWM) modes. For the normal and
clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the
update of the OCR0x compare registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR0x buffer register, and if double buffering is disabled the CPU will access the OCR0x directly.
15.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force
output compare (FOC0x) bit. Forcing compare match will not set the OCF0x flag or reload/clear the timer, but the OC0x pin
will be updated as if a real compare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set,
cleared or toggled).
15.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 register will block any compare match that occur in the next timer clock cycle, even
when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an
interrupt when the Timer/Counter clock is enabled.
OCFnx (Int. Req.)
= (8-bit Comparator)
OCRnx
Waveform Generator
TCNTn
OCnx
top
bottom
FOCn
WGMn1:0
COMnX1:0
DATA BUS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB9AF312KPMC1-G-JNE2 | 功能描述:ARM? Cortex?-M3 FM3 MB9A310K Microcontroller IC 32-Bit 40MHz 160KB (160K x 8) FLASH 52-LQFP (10x10) 制造商:cypress semiconductor corp 系列:FM3 MB9A310K 包装:托盘 零件状态:有效 核心处理器:ARM? Cortex?-M3 核心尺寸:32-位 速度:40MHz 连接性:CSIO，I2C，LIN，UART/USART，USB 外设:DMA，LVD，POR，PWM，WDT I/O 数:36 程序存储容量:160KB（160K x 8） 程序存储器类型:闪存 EEPROM 容量:- RAM 容量:16K x 8 电压 - 电源（Vcc/Vdd）:2.7 V ~ 5.5 V 数据转换器:A/D 8x12b 振荡器类型:内部 工作温度:-40°C ~ 105°C（TA） 封装/外壳:52-LQFP 供应商器件封装:52-LQFP（10x10） 标准包装:160 |
| MB9AF312KPMC-ES-E1 | 制造商:FUJITSU 功能描述: |
| MB9AF312KPMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB9AF312KPMC-G-JNE2 | 功能描述:ARM? Cortex?-M3 FM3 MB9A310K Microcontroller IC 32-Bit 40MHz 160KB (160K x 8) FLASH 48-LQFP (7x7) 制造商:cypress semiconductor corp 系列:FM3 MB9A310K 包装:托盘 零件状态:有效 核心处理器:ARM? Cortex?-M3 核心尺寸:32-位 速度:40MHz 连接性:CSIO，I2C，LIN，UART/USART，USB 外设:DMA，LVD，POR，PWM，WDT I/O 数:36 程序存储容量:160KB（160K x 8） 程序存储器类型:闪存 EEPROM 容量:- RAM 容量:16K x 8 电压 - 电源（Vcc/Vdd）:2.7 V ~ 5.5 V 数据转换器:A/D 8x12b 振荡器类型:内部 工作温度:-40°C ~ 105°C（TA） 封装/外壳:48-LQFP 供应商器件封装:48-LQFP（7x7） 标准包装:250 |
| MB9AF312KQN-ES-AWE2 | 制造商:FUJITSU 功能描述: |
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