参数资料
型号: MC13892VLR2
厂商: Freescale Semiconductor
文件页数: 41/158页
文件大小: 0K
描述: IC PMU I.MX51/37/35/27 186MAPBGA
标准包装: 1,000
应用: 电池管理,显示器(LED 驱动器),手持/移动设备,电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 186-LFBGA
供应商设备封装: 186-PBGA(12x12)
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
Table 8. Register Set
Register
Register
Register
Register
12
13
14
15
Unused
Power Control 0
Power Control 1
Power Control 2
28
29
30
31
Switchers 4
Switchers 5
Regulator Setting 0
Regulator Setting 1
44
45
46
47
ADC 1
ADC 2
ADC 3
ADC4
60
61
62
63
Test 1
Test 2
Test 3
Test 4
The SPI interface is comprised of the package pins listed in Table 9 .
Table 9. SPI Interface Pin Description
SPI Bus
CLK
MOSI
MISO
CS
Interrupt
INT
Supply
SPIVCC
Description
Clock input line, data shifting occurs at the rising edge
Serial data input line
Serial data output line
Clock enable line, active high
Description
Interrupt to processor
Description
Processor SPI bus supply
SPI INTERFACE DESCRIPTION
The control bits are organized into 64 fields. Each of these 64 fields contains 32-bits. A maximum of 24 data bits are used per
field. In addition, there is one “dead” bit between the data and address fields. The remaining bits include 6 address bits to address
the 64 data fields and one write enable bit to select whether the SPI transaction is a read or a write.
The register set will be to a large extent compatible with the MC13783, in order to facilitate software development.
For each SPI transfer, first a one is written to the read/write bit if this SPI transfer is to be a write. A zero is written to the read/
write bit if this is to be a read command only.
The CS line must remain high during the entire SPI transfer. To start a new SPI transfer, the CS line must go inactive and then
go active again. The MISO line will be tri-stated while CS is low.
To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded at the beginning of the
SPI sequence.
Figure 5. SPI Transfer Protocol Single Read/Write Access
MC13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
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