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| 型号： | MC13892VLR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 46/158页 |
| 文件大小： | 0K |
| 描述： | IC PMU I.MX51/37/35/27 186MAPBGA |
| 标准包装： | 1,000 |
| 应用： | 电池管理，显示器（LED 驱动器），手持/移动设备，电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 186-LFBGA |
| 供应商设备封装： | 186-PBGA（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
I2C INTERFACE
INTERRUPT HANDLING
CONTROL
The MC13892 has interrupt generation capability to inform the system on important events occurring. An interrupt is signaled
to the processor by driving the INT pin high. This is true whether the communication interface is configured for the SPI or I 2 C.
Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each
interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register. This will also cause the interrupt line
to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,
the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor
the option of polling for status from the IC. The IC powers up with all interrupts masked except the USB low-power boot, so the
processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the
interrupt bits of interest. If a masked interrupt bit was already high, the interrupt line will go high after unmasking.
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources.
They are read only, and not latched or clearable.
Interrupts generated by external events are debounced, meaning that the event needs to be stable throughout the debounce
period before an interrupt is generated.
BIT SUMMARY
Table 12 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral
descriptions, refer to the related chapters.
Table 12. Interrupt, Mask and Sense Bits
Trigger DebounceTi
Interrupt
Mask
Sense
Purpose
me
Section
ADCDONEI
ADCBISDONEI
TSI
ADCDONEM
ADCBISDONEM
TSM
–
–
–
ADC has finished requested
conversions
ADCBIS has finished requested
conversions
Touch screen wake-up
L2H
L2H
Dual
0
0
30ms
CHGDETS
Charger detection sense is 1 if
32 ms
CHGDETI
CHGDETM
CHGENS
detected
Charger state sense is 1 if active
Dual
100 ms
USBOVI
CHGREVI
CHGSHORTI
USBOVM
CHGREVM
CHGSHORTM
USBOVS
–
–
VBUS over-voltage
Sense is 1 if above threshold
Charger path reverse current
Charger path short circuit
Dual
L2H
L2H
60 μ s
1.0 ms
1.0 ms
Charger fault detection
00 = Cleared, no fault
CHGFAULTI
CHGFAULTM
CHGFAULTS[1:0]
01 = Charge source fault
L2H
10 ms
10 = Battery fault
11 = Battery temperature
CHGCURRI
CCCVI
BPONI
CHGCURRM
CCCVM
BPONM
CHGCURRS
CCCVS
BPONS
Charge current below threshold
Sense is 1 if above threshold
CCCVI transition detection
BP turn on threshold detection.
Sense is 1 if above threshold.
H2L
Dual
L2H
1.0 ms
100 ms
30 ms
Low battery detect
LOBATLI
LOBATLM
LOBATLS
Sense is 1 if below LOBATL
L2H
0
threshold
BVALIDI
BVALIDM
BVALIDS
USB B-session valid
Sense is 1 if above threshold
Dual
L2H: 20-
24 ms
H2L: 8-
12 ms
MC13892
Analog Integrated Circuit Device Data
46
Freescale Semiconductor
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