MC145572
4–26
MOTOROLA
Activation Timer Disable
When this write–only bit is 0, the activation timer operates normally. During activation the timer will
time for approximately 15 seconds, and then the Activation Timer Expire bit will become 1, and the
activation state machine will react to the time–out. When this bit is set to 1, the activation timer is
disabled and the Activation Timer Expire will always read back as 0.
Activation State 6:0
These read–only bits contain the current state of the internal activation controller. Activation State
6, BR11(b7) indicates cold start mode when it is 0 and indicates warm start mode when it is 1.
Activation Timer Expire
This bit shows the status of the activation timer. A 1 indicates that the activation timer has expired.
This register is read–only/write–only. The write only portion controls the U–interface transceiver’s
internal CPU and activation controller. The read portion contains the eight most significant bits of the
Error Power Indicator (EPI) register in the CPU. By setting BR14(b6) to 1, the external microcontroller
can read back the setting of the control bits. These bits are cleared on a Hardware Reset (RESET)
or Software Reset (NR0(b3)). This register is replaced by OR12 when BR10(b1) = 1.
CAUTION
Reserved bit b1 should be set to 0 at all times to maintain future compatibility.
b7
b6
b5
b4
b3
b2
b1
b0
BR12
Activation
Control
Register
Interpolate
Enable
Load
Activation
State
Step
Activation
State
Hold
Activation
State
Big Jump
Select
Reserved
Force
Linkup
wo
wo
wo
wo
wo
wo
wo
wo
EPI 18
EPI 17
EPI 16
EPI 15
EPI 14
EPI 13
EPI 12
EPI 11
ro
ro
ro
ro
ro
ro
ro
ro
Activation Control Steer
When this bit is 0, the internal CPU of the MC145572 has total control of its peripherals, and has
them perform a normal activation procedure. However, when this bit is set to 1, the internal CPU and
its peripherals are directed to use the control information provided in the Interpolate Enable bit in this
register (b6), BR13, BR15A(b7), and BR15A(b6).
Interpolate Enable
This bit is active only when the Activation Control Steer bit (b7) is set to 1. The timing interpolator
is enabled when this bit is 1 and the transceiver is operating in LT mode. The timing interpolator is
disabled when this bit is 0 and the transceiver is operating in LT mode.
Load Activation State
When this bit is set to 1, Activation Control 6:0 is loaded into the activation controller as the new state.
The load is performed at a time that does not adversely affect the operation of the CPU, and will take
place within 1 baud of setting this bit to 1. To load an activation state, this bit must initially be 0. The
desired state should then be loaded into BR11 and this bit should be set to 1. Loading overrides the
setting of the Hold Activation State bit (b3).
Step Activation State
When this bit is set to 1, the activation controller advances to its next state based on its current inputs.
The step is performed at a time that does not adversely affect the operation of the CPU. This bit must
be returned to 0 following the step, to prepare for subsequent steps. Stepping overrides the Hold
Activation State bit (b3). Note that the step will not occur unless the CPU has determined that a
condition for continuing to the next activation state has been satisfied.