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参数资料
| 型号： | MC33580BAPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 12/38页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HI SIDE 15MOHM 24PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | SPI |
| 输出数： | 4 |
| 导通状态电阻： | 15 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ V PWR ≤ 27 V, 4.5 V ≤ V DD ≤ 5.5 V, - 40 ° C ≤ T A ≤ 125 ° C, GND = 0 V unless
otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
f SPI
–
–
3.0
MHz
Required Low State Duration for
RST (26)
t WRST
–
50
350
ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
(27)
t CS
–
–
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
(27)
t ENBL
–
–
5.0
μ s
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
(27)
t LEAD
–
50
167
ns
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
(27)
(27)
t WSCLKh
t WSCLKl
–
–
–
–
167
167
ns
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
(27)
t LAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
(28)
(28)
t SI (SU)
t SI (HOLD)
–
–
25
25
83
83
ns
ns
SO Rise Time
t RSO
ns
C L = 200 pF
SO Fall Time
C L = 200 pF
t FSO
–
–
25
25
50
50
ns
SI, CS , SCLK, Incoming Signal Rise Time (28)
t RSI
–
–
50
ns
SI, CS , SCLK, Incoming Signal Fall Time
(28)
t FSI
–
–
50
ns
Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
(29)
(30)
t SO(EN)
t SO(DIS)
–
–
–
65
145
145
ns
ns
Time from Rising Edge of SCLK to SO Data Valid
(31)
t VALID
ns
0.2 V DD ≤ SO ≤ 0.8 V DD , C L = 200 pF
–
65
105
Notes
26.
27.
28.
29.
30.
31.
RST low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 33580 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS , and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 k ? on pullup on CS .
Time required for output status data to be terminated at SO. 1.0 k ? on pullup on CS .
Time required to obtain valid data out from SO following the rise of SCLK.
33580
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
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