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参数资料
| 型号： | MC33580BAPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 23/38页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HI SIDE 15MOHM 24PQFN |
| 标准包装： | 1,200 |
| 类型： | 高端 |
| 输入类型： | SPI |
| 输出数： | 4 |
| 导通状态电阻： | 15 毫欧 |
| 电源电压： | 6 V ~ 27 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses and their impact on device operation.
ADDRESS 00000 — STATUS REGISTER (STATR_S)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
Each output can be configured to different levels. In
addition to protecting the device, this slow blow fuse
emulation feature can be used to optimize the load
requirements matching system characteristics. Bits D2 : D0
set the overcurrent low detection level to one of eight possible
levels, as shown in Table 11 , page 23 . Bit D3 sets the
overcurrent high detection level to one of two levels, as
Table 11. Overcurrent Low Detection Levels
data. In addition to the device status, this feature provides the
ability to read the content of the OCR0, OCR1, SOCHLR,
CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to
the section entitled Serial Output Communication (Device
Status Return Data) beginning on page 25 .)
SOCL2_s * SOCL1_s * SOCL0_s *
(D2) (D1) (D0)
0 0 0
Overcurrent Low
Detection (Amperes)
HS0 to HS3
18.2
ADDRESS 00001— OUTPUT CONTROL REGISTER
(OCR0 )
The OCR0 register allows the MCU to control the ON / OFF
state of four outputs through the SPI. Incoming message bit
D3 : D0 reflects the desired states of the four high-side
outputs (INx_SPI), respectively. A logic [1] enables the
corresponding output switch and a logic [0] turns it OFF.
ADDRESS 01001— OUTPUT CONTROL REGISTER
(OCR1 )
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
16.3
14.4
12.5
10.5
8.6
6.7
4.8
Incoming message bits D3 : D0 reflect the desired output
that will be mirrored on the Current Sense (CSNS) pin. A
logic [1] on message bits D3 : D0 enables the CSNS pin for
outputs HS3 : HS0, respectively. In the event the current
sense is enabled for multiple outputs, the current will be
* “_s” refers to the output, which is selected through bits D12 : D11;
Table 12. Overcurrent High Detection Levels
summed. In the event that bits D3 : D0 are all logic [0], the
output CSNS will be tri-stated. This is useful when several
CSNS pins of several devices share the same A /D converter.
ADDRESS A 1 A 0 010 — SELECT OVERCURRENT
HIGH AND LOW REGISTER (SOCHLR_S)
SOCH_s * (D3)
0
1
Overcurrent High Detection (Amperes)
HS0 to HS3
100
70
The SOCHLR_s register allows the MCU to configure the
output overcurrent low and high detection levels,
respectively. Each output “s” is independently selected for
configuration based on the state of the D12 : D11 bits
Table 10. Output Selection
* “_s” refers to the output, which is selected through bits D12 : D11;
ADDRESS A 1 A 0 011 — CURRENT DETECTION TIME
AND OPEN LOAD REGISTER (CDTOLR)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an overcurrent low
A 1 (D12)
0
0
1
1
A 0 (D11)
0
1
0
1
HS_s
HS0
HS1
HS2
HS3
condition before an output latches OFF. Each output is
independently selected for configuration based on A 1 A 0 ,
33580
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
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