参数资料
型号: MC33970DWR2
厂商: Freescale Semiconductor
文件页数: 18/36页
文件大小: 0K
描述: IC GAUGE DRIVER SPI 24-SOIC
标准包装: 1
应用: 步进电机驱动器,2 相
输出数: 2
电流 - 输出: 100mA
电压 - 负载: 6.5 V ~ 26 V
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The bits in Table 12 are write-only .
RC12:RC11 (D12:D11) — These bits, along with RC3:RC0
Table 13. RTZCR Full Step Time
(D3:D0) and RC4 (D4), determine the full step time and,
therefore, the rate at which the pointer will move during an
RTZ event. The values of D12:D11 determine the multiplier
(M) is used in equation (1) (refer to page 17 ).
RC12:RC11 = M
? 00 = 1
? 01 = 2
? 10 = 4
? 11 = 8 (Not to be used for design)
RC10:RC5 (D10:D5) — These bits determine the value
preloaded into the RTZ integration accumulator to adjust the
detection threshold. Values range from -1 (00000000) to -
1099 (11111111) as shown in Table 14 .
RC4 (D4) — This bit determines the RTZ blanking time
( blanking ( t) ).
? 0 = 512 μ s
? 1 = 768 μ s
RC3:RC0 (D3:D0) — These bits, along with RC12:RC11
(D12:D11) and RC4 (D4), determine the time variables used
to calculate the full step times with equations (1) or (2)
illustrated above. RC3:RC0 determines the ? t time. The ? t
values range from 0 (0000) to 61.440 ms (1111) and are
shown in Table 13 . The default ? t is 0 (0011).
RC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RC2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
? t (ms)
0
4.096
8.192
12.288
16.384
20.480
24.576
28.672
32.768
36.864
40.960
45.056
49.152
53.248
57.344
61.440
Note Equation (2) (refer to page 17 ) is only used to
calculate the full step time if RC3:RC0 = 0000. Use
equation (1) for all other combinations of RC3:RC0.
Table 14. RTZCR Accumulator Offset
RC10
0
0
0
0
0
.
.
.
1
RC9
0
0
0
0
0
.
.
.
1
RC8
0
0
0
0
0
.
.
.
1
RC7
0
0
0
0
1
.
.
.
1
RC6
0
0
1
1
0
.
.
.
1
RC5
0
1
0
1
0
.
.
.
1
Preload Value
(PV)
0
1
2
3
4
.
.
.
63
Initial Accumulator
Value = (-16 x PV) -1
-1
-17
-33
-49
-65
.
.
.
-1009
SO Communication
When the CS pin is pulled low, the internal status register,
as configured with the PECCR command bits PE11:PE8, is
loaded into the output register and the data is clocked out
MSB (OD15) first. Following a CS transition 0 to 1, the device
determines if the shifted-in message was of a valid length (a
valid message length is one that is greater than 0 bits and a
multiple of 16 bits), and if so, latches the incoming data into
the appropriate registers.
At this time, the SO pin is tri-stated and the status register
is now able to accept new status information. Fault status
information will be latched and held until the Device Status
Output register is selected and it is clocked out via the SO. If
the message length was determined to be invalid, the fault
information will not be cleared and will be transmitted again
during the next valid SPI message. Pointer status information
bits (e.g., pointer position, velocity, and commanded position
status) will always reflect the real time state of the pointer.
33970
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
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