参数资料
| 型号： | MC33970DWR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 7/36页 |
| 文件大小： | 0K |
| 描述： | IC GAUGE DRIVER SPI 24-SOIC |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器，2 相 |
| 输出数： | 2 |
| 电流 - 输出： | 100mA |
| 电压 - 负载： | 6.5 V ~ 26 V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V < V DD < 5.25 V, -40°C < T A < 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT AND CLOCK TIMINGS
SIN, COS Output Turn ON Delay Time (Time from Rising CS Enabling
Outputs to Steady State Coil Voltages and Currents) (14)
SIN, COS Output Turn OFF Delay Time (Time from Rising CS Disables
Outputs to Steady State Coil Voltages and Currents) (14)
Uncalibrated Oscillator Cycle Time
t DLY (ON)
t DLY (OFF)
t CLU
–
–
0.65
–
–
1.0
1.0
1.0
1.7
ms
ms
μ s
Calibrated Oscillator Cycle Time
t CLC
μ s
Cal Pulse = 8.0 μ s, PECCR D4 = Logic [0]
Cal pulse = 8.0 μ s, PECCR D4 = Logic [1]
1.0
0.9
1.1
1.0
1.2
1.1
Maximum Pointer Speed (15)
Maximum Pointer Acceleration (15)
V MAX
A MAX
–
–
–
–
400
4500
°/s
°/s 2
SPI INTERFACE TIMING (16)
Recommended Frequency of SPI Operation
f SPI
–
1.0
3.0
MHz
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
t LEAD
t LAG
–
–
50
50
167
167
ns
ns
SI to Falling Edge of SCLK (Required Setup Time)
t S ISU
–
25
83
ns
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
t WSCLKH
t WSCLKL
–
–
–
–
167
167
ns
ns
Falling Edge of SCLK to SI (Required Hold Time)
t SI (HOLD)
–
25
83
ns
SO Rise Time
t R SO
ns
C L = 200 pF
SO Fall Time
C L = 200 pF
t F SO
–
–
25
25
50
50
ns
SI, CS , SCLK, Incoming Signal Rise Time
t RSI
–
–
50
ns
SI, CS , SCLK, Incoming Signal Fall Time
t F SI
–
–
50
ns
Falling Edge of RST to Rising Edge of RST (Required Setup Time)
t W RST
–
–
3.0
μ s
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
t CS
–
–
5.0
μ s
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
t EN
–
–
5.0
μ s
Notes
14. Maximum specified time for the 33970 is the minimum guaranteed time needed from the microcontroller.
15. The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally
calibrated clock frequency of 1.0 MHz. These are not 100 percent tested.
16. The device shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the temperature
range specified. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device shall
17. The maximum setup time specified for the 33970 is the minimum time needed from the microcontroller to guarantee correct operation.
18. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
19. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes
33970
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
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