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参数资料
| 型号： | MC34704BEPR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 31/54页 |
| 文件大小： | 0K |
| 描述： | IC PWR MNGMT DC-DC MULT 56-QFN |
| 特色产品： | MC34704 Multi-channel Power Management IC (PMIC) |
| 标准包装： | 1 |
| 应用： | 处理器 |
| 电流 - 电源： | 86mA |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘 |
| 供应商设备封装： | 56-QFN-EP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 809 (CN2011-ZH PDF) |
| 其它名称： | MC34704BEPR2DKR |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
processor decision to either shutoff or not, in the mean time
the control loop will try to fix itself.
To avoid erroneous conditions, a 20 μ s filter will be
implemented.
The OV/UV fault flag is masked during DVS until
DVSSTAT flag is asserted “Done”.
To keep the RST output low during ramp up and until the
soft start is done, the OV/UV protection is masked from
reporting that the output is in regulation.
LOGIC COMMANDS AND REGISTERS
I 2 C USER INTERFACE
The 34704 communicates via I 2 C using a default device
address $54 to access all user registers and program all
regulators features independently. Physical address is in a 7-
bit format. The extra bit to complete the 8-bit indicates the
After each byte read or sent, the MC34704 answers with an
Acknowledge bit, indicating the bite was transferred
successfully.
7 bit Physical Address +
(w) bit
1010100 + 0
Start Bit
ACK
0
ACK
Sub-Address
(MSB=0)
0XXXXXXX
ACK
0
ACK
Data
XXXXXXXX
ACK
0
ACK End Bit
1 0 1 0 1
0 0 0
0 0 0 0 0 0 1
0
0 0 0 0 1 1 1 1
Figure 7. Writing sequence I 2 C bit stream
?
7 bit Physical ADD + ACK
(w) bit
Sub-address
(MSB=1)
ACK
RS
Physical
ADD + (r) bit
ACK
Data Read
ACK
1010100 + 0
0
1XXXXXXX
0
1
1010100 + 1
0
XXXXXXX
1
Start Bit
ACK
ACK
ACK
ACK End Bit
1 0 1 0 1 0 0
1 0 0 0 0 0 0
RS 1 0 1 0 1 0 0
0 0 0 1 1 1 1 1
Figure 8. Reading sequence I 2 C bit stream
USER PROGRAMMABLE REGISTERS
GrpC/E power sequencing setting (34704A Only)
The microprocessor can choose one of several voltage
sequence options for the GrpC/E supply (REG5), high
voltage supply (REG6), and negative voltage supply (REG7).
For 3 of the sequencing options, REG5 supply is controlled
and tied with REG6 and REG7 in a preset power sequence.
By default, only REG6 and REG7 are involved in the power
sequence and REG5 is independently controlled with GrpE.
34704A assigns 2 bits to program the GrpC/E power
sequencing options ( CCDSEQ[1:0] ). These bits value is
latched in at GrpC power up and will not be allowed to change
unless a power recycle happens.
OPTION
1
(Default)
MSB
0
LSB
0
GRPC/E ENABLED
REG5 is independently controlled
REG6 and REG7 ramp up together.
GRPC/E DISABLED
REG5 is independently controlled
REG6 and REG7 ramp down together
34704
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
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| MC34708VK | 功能描述:PMIC 解决方案 PMIC 5S 6LDO BST 10BTADC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC34708VKR2 | 功能描述:PMIC 解决方案 PMIC 5S 6LDO BST 10BTADC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC34708VM | 功能描述:PMIC 解决方案 PMIC 5S 6LDO BST 10BtADC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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