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| 型号： | MC34704BEPR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 32/54页 |
| 文件大小： | 0K |
| 描述： | IC PWR MNGMT DC-DC MULT 56-QFN |
| 特色产品： | MC34704 Multi-channel Power Management IC (PMIC) |
| 标准包装： | 1 |
| 应用： | 处理器 |
| 电流 - 电源： | 86mA |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘 |
| 供应商设备封装： | 56-QFN-EP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 809 (CN2011-ZH PDF) |
| 其它名称： | MC34704BEPR2DKR |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
OPTION
2
MSB
0
LSB
1
GRPC/E ENABLED
REG5 ramps up first
GRPC/E DISABLED
REG5, REG6 and REG7 ramp down together
Then REG6 and REG7 ramp up together
3
4
1
1
0
1
REG5, REG6, and REG7 ramp up together
REG5 and REG6 ramp up together first.
REG5, REG6, and REG7 ramp down together
REG7 ramps down first.
Then ramp up REG7
Switching frequency for REG6, 7 & 8
F SW2 can be selected to be between 250 kHz and 1.0 MHz
in 250 kHz steps. On the 34704B, FSW2 is just for REG8
since REG6 and 7 do not exist in this device.
34704 assigns 2 bits to program F SW2 ( F SW2 [1:0] )
Then REG5 and REG6 ramp down together
can decide whether to shutdown the output or not. In the
mean time, the concerned output control loop will be
attempting to correct the error.
Response A and Response B share the same flag bit
FSW2
500kHz (Default)
250kHz
MSB
0
0
LSB
0
1
34704 assigns 1 bit for this function ( OVUVSETx ) where x
corresponds to each regulator.
750kHz
1000kHz
Shutdown Hold (Delay) Time
1
1
0
1
OV/UV Response
A (Default)
B
bit
0
1
The 34704 assigns 2 bits ( SDDELAY[1:0] ) for the
processor to program the shutdown delay time period
Dynamic Voltage Scaling for each regulator
The customer can adjust each regulator’s output
dynamically with 2.5% step size. The total range of
Shutdown Delay
1.0sec (Default)
0.5sec
MSB
0
0
LSB
0
1
adjustability will vary depending on each regulator to
accommodate different operating environments. Some
regulators will utilize the full range of -20.00% to +17.50%
and some regulators will only use the range of ± 10.00%. For
1.5sec 1 0
2.0sec 1 1
Please refer to the /ONOFF pin description for more
details
Programming 34704 response to under-voltage/over-
voltage conditions on each regulator
There are two responses that can be programmed for an
over-voltage/under-voltage condition:
Response A : When an over-voltage (under-voltage) event
is detected, the concerned output shuts down and a register
is flagged to alert the processor.
Response B : When an over-voltage/under-voltage event
is detected, the concerned output will not shutdown, but the
register is flagged to alert the processor. Then, the processor
details, see each regulator’s section. Each 2.5% step takes
50 μ s before moving to the next step. REG8 only performs
DVS when in voltage regulation mode.
During DVS, the Over-voltage and Under-voltage
monitoring will not be active. In addition to that, these faults
will be masked and not active for a DVS settling time period
equal to 1ms. This DVS settling time will start after the
DVSSTAT register is flagged indicating that the DVS cycle is
done. This is to ensure that during DVS and soft start alike
the output will not be tripped due to a momentary over-
voltage or under-voltage fault. This is the same for Response
A and Response B of the over-voltage/under-voltage fault
monitoring.
34704 assigns 4 bits register to program the Dynamic
Voltage Scaling for each regulator ( DVSSETx[3:0] ) where x
corresponds to each regulator.
34704
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
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