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| 型号： | MC34704BEPR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 35/54页 |
| 文件大小： | 0K |
| 描述： | IC PWR MNGMT DC-DC MULT 56-QFN |
| 特色产品： | MC34704 Multi-channel Power Management IC (PMIC) |
| 标准包装： | 1 |
| 应用： | 处理器 |
| 电流 - 电源： | 86mA |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘 |
| 供应商设备封装： | 56-QFN-EP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 809 (CN2011-ZH PDF) |
| 其它名称： | MC34704BEPR2DKR |
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The 34704 assigns 1 bit for each regulator ( TSDFx ) to
indicate a fault due to thermal limit, where x corresponds to
each regulator from REG1 to REG8, except REG7
REG7 Independent ON/OFF Control (Only on 34704A)
The 34704B provide two register to independently turn on
REG7 when REG6 is not needed. Care must be taken when
turning on REG7 to avoid inrush currents during regulator
TSDF
False
True
bit
0
1
ramp-up. Following Process must be followed to assure
successful turn on of REG7.
1. Set EN0 and clear DISCHR_B on REG7CR0 register
2. After 1ms or more, set EN1 on REG7CR0 register
Regulator Fault Register
The 34704 assigns 1 bit for each regulator ( FAULTx ) to
indicate that a fault had occurred on each regulator. The
processor can just access this register periodically to
determine system status. This reduces the access cycles. If
a regulator fault register asserted, then the processor can
access that regulator’s registers to see what kind of fault had
3. Set REG7DAC register to $00
4. Gradually shift up REG7DAC register from $00 to $D9
to ramp-up the output voltage in a soft-start like wave.
Soft start timing is dependant of I2C communication
speed and number of bit you change per writing, for
instance use 4,8 or 16 bits increase to ramp up the
output voltage.
occurred.
1
Register Address
$58
Code
$50
FAULT
False
True
bit
0
1
2
3
4
5
$58
$59
$59
$59
$D0
$00
$04
$08
SPECIAL REGISTERS
REG3 Fine Voltage Scaling Register
Regulator 3 has an additional fine output voltage scaling
that enables to lower the output voltage in 0.5% steps. The
6
...
55
$59
...
$59
$0C
...
$D9
34704 assigns an 8-bit register (REG3DAC) to the REG3
Digital to analog converter for the FB3 voltage generation.
Output votlage must be reduced gradually to avoid a OV/UV
fault to occur.
REGISTER DESCRIPTION SUMMARY TABLE
REG7 independent start up example
Register
GENERAL1
GENERAL2
GENERAL3
VGSET1
VGSET2
REG2SET1
ADDR
$01
$02
$03
$04
$05
$06
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Bit Name
CCDSEQ
SDDELAY
ONOFFx
ALLOFF
SSTIME
COLDF
SHTD
OVUVSET1
DVSSET1
DVSSTAT1
-
OVUVSET2
DVSSET2
Bits
1:0
3:2
3:0
4
1:0
3
4
0
4:1
0
5:1
0
4:1
Description
GrpC/E power sequence selection
Hard shutdown delay timer selection
GrpA,C,D,E On/off bits
Soft shutdown bit (turn off all regulators)
Soft start configuration latch
Cold power up detection flag
Hard Shutdown detection flag
Set REG1/VG response type to OV/UV
REG1 DVS value setting
DVS voltage level status flag
REG1 fault flags: Thermal SD, SC, ILim, UV and OV
Set REG2 response type to OV/UV
REG2 DVS value setting
34704
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
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