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| 型号： | MC34704BEPR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 43/54页 |
| 文件大小： | 0K |
| 描述： | IC PWR MNGMT DC-DC MULT 56-QFN |
| 特色产品： | MC34704 Multi-channel Power Management IC (PMIC) |
| 标准包装： | 1 |
| 应用： | 处理器 |
| 电流 - 电源： | 86mA |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘 |
| 供应商设备封装： | 56-QFN-EP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 809 (CN2011-ZH PDF) |
| 其它名称： | MC34704BEPR2DKR |
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FUNCTIONAL DEVICE OPERATION
COMPONENT CALCULATION
Compensating for boost operation:
RB = -----------------------
------------- – 1
? L: A boost power stage can be designed to operate in
CCM for load currents above a certain level usually 5 to
15% of full load. The minimum value of inductor to
maintain CCM can be determined by using the following
R1
Vo
V REF
[ Ω ]
procedure:
1. Define I OB as the minimum current to maintain CCM
between 10 to 15% of full load:
? Compensation network. (C1,C2,C3, R2, R3)
For compensating a boost converter, 4 important
frequencies referring to the plant are:
1. Output LC filter cutoff frequency (F LC ):
Vo ( D ) ( 1 – D ) T
[H]
L min ≥ ------------------------------------------
2 π LC
2
2I OB
However the worst case condition for the boost power
stage is when the input voltage is equal to one half of the
output voltage, which results in the Maximum Δ I L , then:
D ′ min
F LC = --------------------------
OUT
[Hz]
L min ≥ ----------------
Vo ( T )
16I OB
[H]
? Where D’ min is the minimum off time percentage given
by:
D ′ min = ----------------------
? COUT: The three elements of output capacitor that
contribute to its impedance and output voltage ripple are
the ESR, the ESL and the capacitance C. The minimum
capacitor value is approximately:
Vin min
Vout max
2. Cutoff frequency due to capacitor ESR:
C OUT ≥ ----------------------------
F ESR = --------------------------------------
Io max D max
Fsw Δ Vo r
[F]
1
2 π ( C OUT ) ESR
[Hz]
? Where Δ VO r is the desired output voltage ripple.
3. The right plane zero frequency:
( D ′ min ) R LOAD
2 π L
? Now calculate the maximum allowed ESR to reach the
desired Δ VO r :
RHP Z
2
= ----------------------------------------
[Hz]
4. Crossover frequency (or bandwidth): select this
Δ Vo r
? ---------------------- + I
? 1 – D max
ESR ≤ -------------------------------------------
Io max ?
OB ?
[ Ω ]
frequency as far away form the RHP Z as much as
possible:
F BW ? ---------------
? R1 and RB:
These two resistors help to set the output voltage to the
RHP Z
6
[Hz]
desire value using a Vref=0.6V, select R1 between 10k and
100K and then calculate RB as follows:
The Type 3 external compensation network will be in
charge of canceling some of these poles and zeros to
achieve stability in the system. The following poles and
zeroes frequencies are provided by the type 3 compensation:
F 2P = ----------
F PO = F BW
F P1 = F ESR
F Z1 = 0.9F LC
F SW
2
F 22 = 1.1F LC
34704
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
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