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参数资料
| 型号： | MC35XS3400DPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 24/46页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HIGH SIDE QUAD 24QFN |
| 标准包装： | 1,200 |
| 类型： | 高端开关 |
| 输出数： | 4 |
| Rds（开）： | 35 毫欧 |
| 内部开关： | 是 |
| 电流限制： | 6A |
| 输入电压： | 6 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 8. Output PWM Switching Delay
FAIL-SAFE MODE
The 35XS3400 is in Fail-safe mode when:
Delay bits
000
001
010
011
100
101
Output delay
no delay
16 PWM clock periods
32 PWM clock periods
48 PWM clock periods
64 PWM clock periods
80 PWM clock periods
? V PWR is within the normal voltage range,
? wake-up = 1,
? fail = 1,
? fault = 0.
Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or IN_ON[0:3] or
110 96 PWM clock periods
111 112 PWM clock periods
The clock frequency from IN0 is permanently monitored in
order to report a clock failure in case of the frequency is out
a specified frequency range (from f IN0(LOW) to f IN0(HIGH) ). In
case of clock failure, no PWM feature is provided, the On bit
defines the outputs state and the CLOCK_fail bit reports [1].
Calibratable Internal Clock
The internal clock can vary as much as +/-30 percent
corresponding to typical f PWM(0) output switching period.
Using the existing SPI inputs and the precision timing
reference already available to the MCU, the 35XS3400
allows clock period setting within ? 10 percent of accuracy.
Calibrating the internal clock is initiated by defined word to
CALR register. The calibration pulse is provided by the MCU.
The pulse is sent on the CS pin after the SPI word is
RST input pin transitions from logic [0] to logic [1]. The WAKE
input is capable of being pulled up to VPWR with a series of
limiting resistance limiting the internal clamp current
according to the specification.
The watchdog timeout is a multiple of an internal oscillator .
As long as the WD bit (D15) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally.
Fail Safe Conditions
If an internal watchdog time-out occurs before the WD bit
for FSI open ( Table 9 ) or in case of V DD failure condition
(V DD < V DD(FAIL) )) for VDD_FAIL_en bit is set to logic [1], the
device will revert to a Fail-safe mode until the WD bit is written
to logic [1] (see fail-safe to normal mode transition paragraph)
and V DD is within the normal voltage range.
Table 9. SPI Watchdog Activation
launched. At the moment, the CS pin transitions from logic [1]
to [0] until from logic [0] to [1] determine the period of internal
clock with a multiplicative factor of 128.
Typical RFSI ( ? )
0 (shorted to ground)
(open)
Watchdog
Disabled
Enable
During the Fail-safe mode, the outputs will depend on the
corresponding input. The SPI register content is reset to their
CS
default value (except POR bit) and fault protections are fully
operational.
The Fail-safe mode can be detected by monitoring the NM
bit is set to [0].
SI
CALR
SI command
ignored
NORMAL & FAIL SAFE MODE TRANSITIONS
Transition Fail-safe to Normal mode
Internal
clock duration
In case of negative CS pulse is outside a predefined time
range (from t CSB(MIN) to t CSB(MAX) ), the calibration event will
be ignored and the internal clock will be unaltered or reset to
default value (f PWM(0) ) if this was not calibrated before.
The calibratable clock is used, instead of the clock from
To leave the Fail-safe mode, V DD must be in nominal
voltage and the microcontroller has to send a SPI command
with WDIN bit set to logic [1]; the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode (auto-retry included).
Moreover, the device can be brought out of the Fail-safe
mode due to watchdog timeout issue by forcing the FSI pin to
logic [0].
IN0 input, when CLOCK_sel is set to [1].
Transition Normal to Fail-Safe Mode
To leave the Normal mode, a Fail-safe condition must
occurred (fail=1). The previous latched faults are reset by the
transition into Fail-safe mode (autoretry included).
35XS3400
Analog Integrated Circuit Device Data ?
24
Freescale Semiconductor
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