参数资料
型号: MC56F8322VFAER2
厂商: Freescale Semiconductor
文件页数: 53/136页
文件大小: 0K
描述: IC HYBRID CTRLR 16BIT 48-LQFP
标准包装: 2,000
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 60MHz
连通性: CAN,SCI,SPI
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 21
程序存储器容量: 40KB(20K x 16)
程序存储器类型: 闪存
RAM 容量: 6K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 带卷 (TR)
配用: MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
Signal Pins
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
23
Preliminary
MOSI0
(GPIOB2)
18
Schmitt
Input/
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
SPI 0 Master Out/Slave In — This serial data pin is an output from a
master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is MOSI0.
MISO0
(RXD1)
(GPIOB1)
16
Schmitt
Input/
Output
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
Receive Data — SCI1 receive data input
Port B GPIO - This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is MISO0.
SS0
(TXD1)
(GPIOB0)
15
Schmitt
Input
Schmitt
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Slave Select — SS0 is used in slave mode to indicate to the
SPI module that the current transfer is to be received.
Transmit Data — SCI1 transmit data output
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is SS0.
PWMA0
(GPIOA0)
3Schmitt
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA0 — This is one of six PWMA output pins.
Port A GPIO — This GPIO pin can be individually programmed as an
input or output pin.
In the 56F8322, the default state after reset is PWMA0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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