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参数资料
型号： MC56F8323VFBE
厂商： Freescale Semiconductor
文件页数： 34/140页
文件大小： 0K
描述： IC MPU HYBRID DSP 32K 64-LQFP
标准包装： 160
系列： 56F8xxx
核心处理器： 56800E
芯体尺寸： 16-位
速度： 60MHz
连通性： CAN，SCI，SPI
外围设备： POR，PWM，温度传感器，WDT
输入/输出数： 27
程序存储器容量： 32KB（16K x 16）
程序存储器类型： 闪存
RAM 容量： 12K x 8
电压 - 电源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
数据转换器： A/D 8x12b
振荡器型： 内部
工作温度： -40°C ~ 105°C
封装/外壳： 64-LQFP
包装： 托盘
配用： MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
Equivalent Circuit for ADC Inputs
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
129
Preliminary
10.16 Equivalent Circuit for ADC Inputs
Figure 10-22 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (VREFH-VREFLO)/2, while the other charges to the analog input voltage. When the
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (VREFH-VREFLO)/2. The switches switch
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, VREF and the ADC clock frequency.
1.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf
3.
Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms
4.
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1pf
Figure 10-22 Equivalent Circuit for A/D Loading
10.17 Power Consumption
See Part 10 for a list of IDD requirements for the 56F8323. This section provides additional detail which
can be used to optimize power consumption for a given application.
Power consumption is given by the following equation:
A, the internal [static component], is comprised of the DC bias currents for the oscillator, current, PLL,
and voltage references. These sources operate independently of processor state or operating frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
Total power =
A: internal [static component]
+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static]
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(VREFH - VREFLO)/2
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