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参数资料
型号： MC56F8323VFBE
厂商： Freescale Semiconductor
文件页数： 54/140页
文件大小： 0K
描述： IC MPU HYBRID DSP 32K 64-LQFP
标准包装： 160
系列： 56F8xxx
核心处理器： 56800E
芯体尺寸： 16-位
速度： 60MHz
连通性： CAN，SCI，SPI
外围设备： POR，PWM，温度传感器，WDT
输入/输出数： 27
程序存储器容量： 32KB（16K x 16）
程序存储器类型： 闪存
RAM 容量： 12K x 8
电压 - 电源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
数据转换器： A/D 8x12b
振荡器型： 内部
工作温度： -40°C ~ 105°C
封装/外壳： 64-LQFP
包装： 托盘
配用： MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
56F8323 Technical Data, Rev. 17
20
Freescale Semiconductor
Preliminary
VCAP1
57
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
connect each pin to a 2.2
μF or greater bypass capacitor in order to
bypass the core logic voltage regulator, required for proper chip
operation.
When OCR_DIS is tied to VDD, (regulator disabled), these pins
become VDD_CORE and should be connected to a regulated 2.5V
power supply.
Note: This bypass is required even if the chip is powered with
an external supply.
VCAP2
23
VCAP3
5
VCAP4
43
OCR_DIS
45
On-Chip Regulator Disable —
Tie this pin to VSS to enable the on-chip regulator
Tie this pin to VDD to disable the on-chip regulator
This pin is intended to be a static DC signal from power-up to
shut down. Do not try to toggle this pin for power savings
during operation.
EXTAL
(GPIOC0)
46
Input
Schmitt
Input/
Output
Input
External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to VSS.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is an EXTAL input with pull-ups disabled.
XTAL
(GPIOC1)
47
Output
Schmitt
Input/
Output
Crystal Oscillator Output — This output can be connected to an
8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to VSS.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is an XTAL input with pull-ups disabled.
TCK
53
Schmitt
Input
Input,
pulled low
internally
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resistor. A Schmitt
trigger input is used for noise immunity.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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