参数资料
型号: MC56F8323VFBE
厂商: Freescale Semiconductor
文件页数: 63/140页
文件大小: 0K
描述: IC MPU HYBRID DSP 32K 64-LQFP
标准包装: 160
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 60MHz
连通性: CAN,SCI,SPI
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 27
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 12K x 8
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 64-LQFP
包装: 托盘
配用: MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
Signal Pins
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
29
Preliminary
TC0
(TXD0)
(GPIOC6)
1Schmitt
Input/
Output
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
TC0 — Timer C, Channel 0
Transmit Data — SCI0 transmit data output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC0.
TC1
(RXD0)
(GPIOC5)
64
Schmitt
Input/
Output
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
TC1 — Timer C, Channel 1
Receive Data — SCI0 receive data input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC1.
TC3
(GPIOC4)
63
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
TC3 — Timer C Channel 3
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC3.
IRQA
(VPP)
12
Schmitt
Input
Input,
pull-up
enabled
External Interrupt Request A — The IRQA input is an
asynchronous external interrupt request during Stop and Wait mode
operation. During other operating modes, it is a synchronized
external interrupt request which indicates an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered
VPP — This pin is used for Flash debugging purposes.
RESET
2Schmitt
Input
Input,
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the reset state. A Schmitt trigger input is used for noise immunity.
The internal reset signal will be deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert RESET,
but do not assert TRST.
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Signal Name
Pin No.
Type
State During
Reset
Signal Description
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