8- 12
MC68306 USER'S MANUAL
MOTOROLA
8.10 BUS OPERATION—DRAM ACCESSES AC TIMING
SPECIFICATIONS (The electrical specifications in this document are preliminary. See Figures 8-8–8-11)
16.67 MHz
0-Wait
1-Wait
Num.
Characteristic
Min
Max
Min
Max
Unit
71
CLKOUT High to RAS≈ Asserted (0 Wait State Operation)
0
30
–
ns
71A
AS Asserted to RAS≈ Asserted (0 Wait State Operation)
0
10
–
ns
72
CLKOUT Low to RAS≈ Asserted (1 Wait State Operation)
–
0
25
ns
73
CLKOUT Low to Row
Address Valid
030
ns
74
Row Address Valid to RAS≈ Asserted
15
–
30
–
ns
75
RAS≈ Asserted to Row Address Invalid
20
–
40
–
ns
76
CLKOUT High to Row Address Invalid (0 Wait State Operation)
0–––
ns
77
CLKOUT Low to Row Address Invalid (1 Wait State Operation)
––0–
ns
78
RAS≈ Width Asserted (Non-Page Mode)
120
180
150
210
ns
79
RAS≈ Width Asserted (Page Mode)
480
540
510
570
ns
80
RAS≈ Width Negated (Back to Back Cycles)
60
–
90
–
ns
81
RAS≈ Asserted to CAS≈ Asserted
45
–
60
–
ns
82
CLKOUT High to Column Address
Valid (0 Wait State Operation)
0
30
–
ns
83
CLKOUT Low to Column Address
Valid (1 Wait State Operation)
–
0
30
ns
84
CLKOUT Low to CAS≈ Asserted (0 Wait State Operation)
0
20
–
ns
85
CLKOUT High to CAS≈ Asserted (1 Wait State Operation)
–
0
20
ns
86
Column Address Valid to CAS≈ Asserted
20
–
20
–
ns
87
CAS≈ Asserted to Column Address Invalid
75
–
100
–
ns
88
CAS≈ Width Asserted
60
90
120
ns
89
CLKOUT Low to RAS≈ /CAS≈ Negated
0
30
0
30
ns
89A
AS Negated to RAS≈ /CAS≈ Negated
0
10
0
10
ns
90
CAS≈ Width Negated (Back to Back Cycles)
150
–
180
–
ns
91
CAS≈ Width Negated (Page Mode2)
240
300
240
300
ns
92
UDS/LDS Asserted to CAS≈ Asserted1 (Page Mode 2)
0
10
0
10
ns
93
DRAMW Low to CAS≈ Asserted (Write)
30
–
60
–
ns
94
Data Out Valid to CAS≈ Asserted (Write)
15
–
45
–
ns
95
CLKOUT Low to CAS≈ Asserted (Refresh Cycle)
0
20
0
20
ns
96
CLKOUT High to CAS≈ Negated (Refresh Cycle)
0
20
0
20
ns
97
CAS≈ Width Asserted (Refresh Cycle)
80
120
140
180
ns
98
CAS≈ Asserted to RAS≈ Asserted (Refresh Cycle)
20
60
20
60
ns
99
CLKOUT High to RAS≈ Asserted (Refresh Cycle)
0
30
0
30
ns
100
CLKOUT Low to RAS≈ Negated (Refresh Cycle)
0
25
0
25
ns
101
RAS≈ Width Asserted (Refresh Cycle)
80
120
140
180
ns
102
DRAMW High to RAS≈ Asserted (Refresh Cycle)
20
60
20
60
ns
103
DRAMW High Hold After RAS≈ Asserted (Refresh Cycle)
20
–
20
–
ns
NOTES:
1. On write portion of TAS, CAS assertion is gated by UDS/LDS (not CLKOUT as in all other operation).
2. Page mode is used on Read-Modify-Write (TAS instruction) cycles only.
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Freescale Semiconductor, Inc.
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