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参数资料
| 型号： | MC68HC05P9DWR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 61/88页 |
| 文件大小： | 6557K |
| 代理商： | MC68HC05P9DWR2 |
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8
MOTOROLA
8-4
MC68HC05E0
SERIAL INTERFACE
A START bit is generated on the data line before a data byte is transmitted. No START bit is
generated for receive sequences. The START bit is a low state applied to the data line while the
clock stays in its idle state. The START bit lasts for 1 SPI clock period (determined by BD0 and
BD1 in the SI Mode Register).
The SPI bus allows either 6-bit or 8-bit words to be sent or received. WL (bit 4 in SI Mode Register)
determines the word length (Low = 8-bit, High = 6-bit). When a 6-bit word is to be sent, it should
be written to the 6 most signicant bits of the SI Data Register. After transmission, the location of
the bits in the SI Data Register will have changed. The 6-bit word now resides in bits 0 to 5, and
the upper 2 bits are the remaining (unused) bits. This is because the SI Data Register functions
as a shift register during transmission, and the most signicant bit is shifted round to the least
signicant bit every time a new data bit is sent. Similarly, when receiving a 6-bit word, it will be
located in the lower 6 bits of SI Data Register at the end of the receive sequence.
The direction of data along the data line is determined by R/WB (bit 0 in the SI S Register). R/WB
= 0 sends data to a peripheral, R/WB = 1 receives data from a peripheral.
The Serial Peripheral Interface is congured via the Port E/SI Mode Register ($0010).
SIE —Serial Interrupt Enable Bit
This bit masks the interrupt signal generated at the end of each SPI transfer.
1 (set)
–
Interrupts not masked
0 (clear) –
Interrupts masked
CPOL, CPHA — Clock Polarity and Clock Phase Bits
These two bits provide four possible clock polarity/phase relationships for recognition of valid data,
as shown in Figure 8-2. The MC68HC05E0 SPI is always the master.
The interrupt signal is generated after the last clock pulse. The START bit/STOP bit is
automatically generated (only when sending). A receive sequence only clocks in the data bits sent
from the slave.
WL — Word Length Bit.
This bit determines whether 6-bit or 8-bit data words are to be sent/received.
1 (set)
–
6-bit word length
0 (clear) –
8-bit word length
Note:
In the I2C-bus mode only 8-bit words can be transferred.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port E/SI mode register
$0010
SIE
CPHA
CPOL
WL
BD‘1
BD0
PS1
PS0
0000 0000
70
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