- 您现在的位置：买卖IC网 > PDF目录69027 > MC68HC05P9DWR2 (MOTOROLA INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 PDF资料下载
参数资料
| 型号： | MC68HC05P9DWR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 63/88页 |
| 文件大小： | 6557K |
| 代理商： | MC68HC05P9DWR2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页当前第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页
8
MOTOROLA
8-6
MC68HC05E0
SERIAL INTERFACE
8.3
I2C-Bus Conguration
The I2C-bus protocol was specied by Philips. It consists of a bidirectional data line (SDA) and a
bidirectional clock line (SCL). Each driver connected to the SDA and SCL lines should be
open-drain. An off-chip pull-up resistor (4k7) pulls either line to a high state if the line is not being
held low by an active peripheral. SDA and SCL pulled high is the I2C idle state.
The original I2C-bus specication allows for different devices connected to an SDA and SCL line
to be receivers, transmitters, masters (generating the SCL clock) or slaves. In the MC68HC05E0
implementation, the micro is always master.
A variety of devices exist which can communicate over the I2C-bus, from complex microcontrollers
(e.g. Philips 68070) to real-time clock chips, LCD drivers and “dumb” serial EEPROMs. The
I2C-bus implementation on the MC68HC05E0 is intended for use in simpler bus systems, rather
than complex multi-master systems. For this reason the following features of the full I2C-bus
protocol are NOT supported:
–
The passing of bus mastery from one peripheral to another. (The
MC68HC05E0 is always bus master).
–
Clock synchronization when two bus masters simultaneously drive SCL.
–
Detection of data collision (2 devices sending data simultaneously).
–
Address register and comparator to allow selection of which peripheral is to
be addressed. (No I2C-bus address register is available on the
MC68HC05E0)
The I2C-bus specication calls for a pause of at least 4.7
s between the end of one transmission
sequence and the start of another. This is not done in hardware by the MC68HC05E0 but, as at
least three instructions are needed to load/read, set-up and start the I2C-bus circuit, the pause
will always be greater than 5
s when using a 4 MHz crystal. If an 8 MHz crystal is used, software
must provide a delay greater than 4.7
s. The user has control over whether START and STOP
bits are generated. Also, the I2C-bus can be programmed such that the micro does or does not
provide an acknowledge signal to peripherals.
The I2C-bus circuitry monitors the bus continuously to check that no other I2C-bus peripheral is
currently using the bus.
Figure 8-3 shows the timing relationship between the clock (SCL) and data (SDA) in I2C-bus
mode. Refer to Section 9 for more detailed timing information.
72
相关PDF资料 |
PDF描述 |
|---|---|
| MC68HC05RC18P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05RC18FN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC05SR3FB | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC05SR3CFB | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC05T7B | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC05P9P | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05PV8 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05PV8A | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05RC16 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC16DW | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:General Release Specification |
发布紧急采购，3分钟左右您将得到回复。