- 您现在的位置：买卖IC网 > PDF目录69027 > MC68HC05P9DWR2 (MOTOROLA INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 PDF资料下载
参数资料
| 型号： | MC68HC05P9DWR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 66/88页 |
| 文件大小： | 6557K |
| 代理商： | MC68HC05P9DWR2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页当前第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页
8
MC68HC05E0
MOTOROLA
8-9
SERIAL INTERFACE
IRQACK — Interrupt Acknowledge Flag Bit
This bit is the serial interface interrupt ag, raised at the end of every SPI/I2C-bus transaction.
Writing a zero to IRQACK clears the interrupt ag, resets the interrupt circuitry and permits new
data to be written to the data register or newly received data to overwrite the old data in the
reception register (meaning the data register has already been read).
1 (set)
–
I2C-bus transaction completed
0 (clear) –
No I2C-bus transaction has occurred
NMA — No Master Acknowledge Bit
When set high NMA prevents the MC68HC05E0 from giving an acknowledge signal to a
peripheral after receiving a byte of data. An acknowledge is made if NMA is low.
1 (set)
–
Prevent acknowledgement after data receive
0 (clear) –
Permit acknowledgement after data receive
SP — STOP Bit
If high, an I2C-bus STOP condition is generated on the SDA line at the end of the next bus transfer.
If low, no STOP bit is produced.
1 (set)
–
Generate STOP condition after data transfer
0 (clear) –
Do not generate STOP condition after data transfer
ST — START Bit
If high, an I2C-bus START condition is generated on the SDA line at the beginning of the next bus
transfer. If low, no START bit is produced.
1 (set)
–
Generate START condition before data transfer
0 (clear) –
Do not generate START condition before data transfer
R/WB — Read/Write Bit
This bit selects the direction of the data transfer during SPI or I2C-bus operation.
1 (set)
–
Read (from peripheral)
0 (clear) –
Write (to peripheral)
75
相关PDF资料 |
PDF描述 |
|---|---|
| MC68HC05RC18P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| MC68HC05RC18FN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC05SR3FB | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC05SR3CFB | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC05T7B | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC05P9P | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05PV8 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05PV8A | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Techinal Data - rev 1.9 |
| MC68HC05RC16 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05RC16DW | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:General Release Specification |
发布紧急采购，3分钟左右您将得到回复。