- 您现在的位置：买卖IC网 > PDF目录378662 > MC68HC11G5CFN (MOTOROLA INC) High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller PDF资料下载
参数资料
| 型号： | MC68HC11G5CFN |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller |
| 中文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封装： | PLASTIC, LCC-84 |
| 文件页数： | 56/195页 |
| 文件大小： | 839K |
| 代理商： | MC68HC11G5CFN |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页当前第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页
MOTOROLA
5-4
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC11G5
is supplied, this delay can be inhibited so that processing can be resumed within a few
cycles of a wake-up from STOP mode. When DLY is set, a 4064 E-clock cycle delay is
imposed to allow oscillator stabilization.
CME — Clock Monitor Enable
0 – Clock monitor disabled; a slow clock may be used.
1 – Slow or stopped clocks will cause a clock failure reset sequence.
In order to use both STOP and the clock monitor, the CME bit should be written to zero
prior to executing a STOP instruction and rewritten to one after recovery from STOP.
CR1 and CR0 — COP Timer Rate select bits
The COP system is driven by a constant frequency of E divided by 215. CR1 and CR0
specify an additional divide-by factor to arrive at the COP timeout rate (see Table 5-1).
5.1.6
State After Reset
The MCU mode is a function of the state of the two mode select pins. Enable bits for the ROM and
the COP system are contained in the CONFIG register, which is initialized during reset, and are
dependent on the mode which has been selected. In the single chip, bootstrap and test modes, the
ROM is on; in expanded mode the ROM is off. In the single chip and expanded modes the COP is
on; in bootstrap and test modes the COP is off.
The remainder of the system configuration is controlled via registers. Most of these registers and
control bits are forced to a specific state during reset. If a user requires a different configuration, he
must write different information into these registers.
Most of the configuration state after reset is independent of the MCU mode selected. Those features
which are specifically dependent on the mode are described in the following paragraphs.
CPU — The CPU fetches the restart vector from $FFFE, $FFFF ($BFFE, $BFFF in bootstrap mode
or test mode) during the first two cycles after reset and begins executing instructions. The stack
pointer and other CPU registers are indeterminate immediately after reset, except for the X and I
interrupt mask bits in the CCR, which are set so that interrupt requests will be masked, and the S
bit, also in the CCR, which is set so that the STOP instruction is disabled.
Memory Map — Immediately after reset the internal memory map of the MC68HC11G5 has 16
kilobytes of ROM located at the top of memory from $C000 – $FFFF (except in expanded mode
where the ROM is disabled and these bytes are external accesses), 512 bytes of RAM located at
the bottom of memory ($0000 – $01FF) and 128 bytes of internal register and I/O space located at
($1000 – $107F). If the bootstrap mode is selected, the memory map is the same except for the
addition of a small internal bootstrap ROM which is located at $BF00 – $BFFF. When a vector fetch
occurs in bootstrap mode, the A14 bit is forced low so that the vectors in the bootstrap ROM are
selected. In the test mode, A14 is also forced low during vector fetches but the bootstrap ROM is
not enabled so vectors are fetched from external memory located at $BFC0 – $BFFF.
Parallel I/O — If reset in an expanded mode, the pins used by the parallel I/O functions are dedicated
to the expansion bus and the parallel I/O functions become externally accessed functions to allow
emulation. If reset in single chip mode, the CWOM bit is initialized to zero (Port C not wired-OR
相关PDF资料 |
PDF描述 |
|---|---|
| MC68HLC908LJ12 | Addendum to MC68HC908LJ12 |
| MC68HLC908QT1 | Microcontrollers |
| MC68HLC908QT2 | Microcontrollers |
| MC68HLC908QT4 | Microcontrollers |
| MC68HLC908QY1 | Microcontrollers |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC11G7 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Unit |
| MC68HC11G7CFN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| MC68HC11K0 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC11K0CFN2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11K0CFN3 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:8-Bit Microcontroller |
发布紧急采购，3分钟左右您将得到回复。