![](http://datasheet.mmic.net.cn/120000/MCF54417CMJ250_datasheet_3559710/MCF54417CMJ250_26.png)
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Electrical characteristics
Freescale Semiconductor
26
4.8
Oscillator and PLL electrical characteristics
Reference
Figure 9 for crystal circuits.
Table 14. PLL electrical characteristics
Num
Characteristic
Symbol
Min
Max
Unit
1
PLL Reference Frequency Rang
e1Crystal reference
External reference
fref_crystal
fref_ext
501
1
These reference value ranges are for after a PLL predivider (PREDIV), which can be programmed to 1, 2, 4, 8, or 16.
The PREDIV value can be set while booting from serial flash. In parallel reset configuration, the PREDIV value is set to
one. In this mode, if the input frequency results in an out of range reference frequency, boot the processor in limp
mode, set the proper PREDIV and multiplier settings, and switch to PLL mode.
MHz
2
Core frequency
FB_CLK frequency2 (MISCCR2[FBHALF] = 0)
2
All internal registers retain data at 0 Hz.
fsys
fsys/2
120
60
250
100
MHz
3
VCO frequency
fvco
240
500
MHz
4
DCC frequency3
3 Required only for DDR2 memory.
fDCC
300
500
MHz
5
Crystal start-up time4, 5
4
This parameter is guaranteed by characterization before qualification rather than 100% tested.
5
Proper PC board layout procedures must be followed to achieve specifications.
tcst
—10
ms
6
EXTAL input high voltage
External and limp modes
VIHEXT
EVIH
EVDD
V
7
EXTAL input low voltage
External and limp modes
VILEXT
0EVIL
V
6
This specification is the PLL lock time only and does not include oscillator start-up time.
tlpll
—50
ms
9
Duty cycle of reference
4tdc
–45%
+45%
%
10
Crystal capacitive load
CL
—
From crystal
spec
pF
11
Feedback resistor
RF
10
—
M
12
Series resistor
RS
0
200
13
Discrete load capacitance for XTAL
CL_XTAL
—2
C
L –
CS_XTAL –
CPCB_XTAL
7
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
pF
14
Discrete load capacitance for EXTAL
CL_EXTAL
—2
C
L –
CS_EXTAL –
CPCB_EXTAL
pF
15
FB_CLK period jitter, 4, 5, 7, 8, Measured at fSYS Max Peak-to-peak jitter (clock edge to clock edge)
Long term jitter
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
Cjitter
—
10
0.1
% fsys/3