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参数资料
型号： MCHC11F1CFNE2
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, MICROCONTROLLER, PQCC68
封装： ROHS COMPLIANT AND HALOGEN FREE, PLASTIC, LCC-68
文件页数： 4/162页
文件大小： 4554K
代理商： MCHC11F1CFNE2
SERIAL PERIPHERAL INTERFACE
MOTOROLA
TECHNICAL DATA
8-3
Figure 8-2 SPI Transfer Format
8.2.1 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity using
two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL
control bit, which selects an active high or active low clock, and has no significant ef-
fect on the transfer format. The clock phase (CPHA) control bit selects one of two dif-
ferent transfer formats. The clock phase and polarity should be identical for the master
SPI device and the communicating slave device. In some cases, the phase and polar-
ity are changed between transfers to allow a master device to communicate with pe-
ripheral slaves having different requirements.
When CPHA equals zero, the SS line must be negated and reasserted between each
successive serial byte. Also, if the slave writes data to the SPI data register (SPDR)
while SS is low, a write collision error results.
When CPHA equals one, the SS line can remain low between successive transfers.
8.3 SPI Signals
The following paragraphs contain descriptions of the four SPI signals: master in slave
out (MISO), master out slave in (MOSI), serial clock (SCK), and slave select (SS).
Any SPI output line must have its corresponding data direction bit in DDRD register
set. If the DDR bit is clear, that line is disconnected from the SPI logic and becomes a
general-purpose input. All SPI input lines are forced to act as inputs regardless of the
state of the corresponding DDR bits in DDRD register.
2345678
1
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK CYCLE #
SS (TO SLAVE)
654321
LSB
MSB
654321
LSB
SAMPLE INPUT
DATA OUT
SAMPLE INPUT
DATA OUT
(CPHA = 1)
(CPHA = 0)
SLAVE CPHA = 1 TRANSFER IN PROGRESS
MASTER TRANSFER IN PROGRESS
SLAVE CPHA = 0 TRANSFER IN PROGRESS
3
2
1
5
4
SS ASSERTED
MASTER WRITES
FIRST SCK EDGE
SPIF SET
SS NEGATED
1
2
3
4
5
TO SPDR
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相关代理商/技术参数
参数描述
MCHC11F1CFNE2 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
MCHC11F1CFNE2R 功能描述:8位微控制器 -MCU 8B MCU 1KRAM 512EE RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
MCHC11F1CFNE3 功能描述:8位微控制器 -MCU 8B MCU 1KRAM 512EE RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
MCHC11F1CFNE3 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
MCHC11F1CFNE3R 功能描述:8位微控制器 -MCU 8B MCU 1KRAM 512EE RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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