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参数资料
| 型号： | MCHC11F1CFNE2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, EEPROM, MICROCONTROLLER, PQCC68 |
| 封装： | ROHS COMPLIANT AND HALOGEN FREE, PLASTIC, LCC-68 |
| 文件页数： | 87/162页 |
| 文件大小： | 4554K |
| 代理商： | MCHC11F1CFNE2 |
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CENTRAL PROCESSING UNIT
MC68HC11F1
3-6
TECHNICAL DATA
3.1.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is
zero. Otherwise, the Z bit is cleared. Compare instructions do an internal implied sub-
traction and the condition codes, including Z, reflect the results of that subtraction. A
few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags.
For these operations, only = and - conditions can be determined.
3.1.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation is
negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative if
its most significant bit (MSB) is a one. A quick way to test whether the contents of a
memory location has the MSB set is to load it into an accumulator and then check the
status of the N bit.
3.1.6.5 Interrupt Mask (I)
The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable in-
terrupt sources. While the I bit is set, interrupts can become pending, but the operation
of the CPU continues uninterrupted until the I bit is cleared. After any reset, the I bit is
set by default and can only be cleared by a software instruction. When an interrupt is
recognized, the I bit is set after the registers are stacked, but before the interrupt vector
is fetched. After the interrupt has been serviced, a return from interrupt instruction is
normally executed, restoring the registers to the values that were present before the
interrupt occurred. Normally, the I bit is zero after a return from interrupt is executed.
Although the I bit can be cleared within an interrupt service routine, “nesting” interrupts
in this way should only be done when there is a clear understanding of latency and of
the arbitration mechanism. Refer to SECTION 5 RESETS AND INTERRUPTS.
3.1.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit
during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half carry is
used during BCD operations.
3.1.6.7 X Interrupt Mask (X)
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is set
by default and must be cleared by a software instruction. When an XIRQ interrupt is
recognized, the X and I bits are set after the registers are stacked, but before the in-
terrupt vector is fetched. After the interrupt has been serviced, an RTI instruction is
normally executed, causing the registers to be restored to the values that were present
before the interrupt occurred. The X interrupt mask bit is set only by hardware (RESET
or XIRQ acknowledge). X is cleared only by program instruction (TAP, where the as-
sociated bit of A is zero; or RTI, where bit 6 of the value loaded into the CCR from the
stack has been cleared). There is no hardware action for clearing X.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCHC11F1CFNE2 | 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC |
| MCHC11F1CFNE2R | 功能描述:8位微控制器 -MCU 8B MCU 1KRAM 512EE RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MCHC11F1CFNE3 | 功能描述:8位微控制器 -MCU 8B MCU 1KRAM 512EE RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MCHC11F1CFNE3 | 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC |
| MCHC11F1CFNE3R | 功能描述:8位微控制器 -MCU 8B MCU 1KRAM 512EE RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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