参数资料
型号: MCIMX27LVOP4AR2
厂商: Freescale Semiconductor
文件页数: 77/152页
文件大小: 0K
描述: IC LOW END I.MX27 404-MAPBGA
视频文件: i.MX27 Multimedia Application Processor
标准包装: 1,000
系列: i.MX27
核心处理器: ARM9
芯体尺寸: 32-位
速度: 400MHz
连通性: 1 线,CAN,EBI/EMI,以太网,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外围设备: DMA,LCD,POR,PWM,WDT
程序存储器类型: ROMless
RAM 容量: 45K x 8
电压 - 电源 (Vcc/Vdd): 1.38 V ~ 1.52 V
振荡器型: 外部
工作温度: -20°C ~ 85°C
封装/外壳: 404-LFBGA
包装: 带卷 (TR)
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
30
Freescale Semiconductor
Signal Descriptions
Note: SD3_DATA is multiplexed with ATA_DATA3–0.
UARTs (X6)
UART1_RTS
Request to Send input signal; PE15
UART1_CTS
Clear to Send output signal; PE14
UART1_RXD
Receive Data input signal; PE13
UART1_TXD
Transmit Data output signal, PE12
UART2_RXD
Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP; PE7.
UART2_TXD
Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP; PE6.
UART2_RTS
Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP; PE4.
UART2_CTS
Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP; PE3.
UART3_RTS
Request to Send input signal, PE11
UART3_CTS
Clear to Send output signal; PE10
UART3_RXD
Receive Data input signal; PE9
UART3_TXD
Transmit Data output signal; PE8
Note: UART 4, 5, and 6 are multiplexed with COMS Sensor Interface signals.
Keypad
KP_COL[5:0]
Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and
UART2_TXD respectively. Alternatively, KP_COL6 is also available on the internal factory test
signal TEST_WB2. The Function Multiplexing Control Register in the System Control chapter
must be used in conjunction with programming the GPIO multiplexing (to select the alternate
signal multiplexing) to choose which signal KP_COL6 is available.
KP_ROW[5:0]
Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and
UART2_RXD signals respectively. The Function Multiplexing Control Register in the System
Control chapter must be used in conjunction with programming the GPIO multiplexing (to select
the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are
available.
Note: KP_COL[7:6] and KP_ROW[7:6] are multiplexed with UART2 signals as show above, also see UARTs table.
PWM
PWMO
PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and
TOUT3 of the General Purpose Timer module; PE5.
CSPI (X3)
CSPI1_MOSI
Master Out/Slave In signal, PD31
CSPI1_MISO
Master In/Slave Out signal, PD30
CSPI1_SS[2:0]
Slave Select (Selectable polarity) signal, the CSPI1_SS2 is multiplexed with
USBH2_DATA5/RCV; and CSPI1_SS1 is multiplexed with EXT_DMAGRANT; PD26–28.
CSPI1_SCLK
Serial Clock signal, PD29
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Pad Name
Function/Notes
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