参数资料
型号: MCIMX355AVM4B
厂商: Freescale Semiconductor
文件页数: 107/147页
文件大小: 0K
描述: IC MPU I.MX35 400MAPBGA
标准包装: 90
系列: i.MX35
核心处理器: ARM11
芯体尺寸: 32-位
速度: 400MHz
连通性: 1 线,CAN,EBI/EMI,以太网,I²C,MMC,SPI,SSI,UART/USART,USB OTG
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 96
程序存储器类型: ROMless
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.22 V ~ 1.47 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 400-LFBGA
包装: 托盘
i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
62
4.9.8
Fast Ethernet Controller (FEC) AC Electrical Specifications
This section describes the electrical information of the FEC module. The FEC is designed to support both
10- and 100-Mbps Ethernet networks. An external transceiver interface and transceiver function are
required to complete the interface to the media. The FEC supports the 10/100 Mbps Media Independent
Interface (MII) using a total of 18 pins. The 10-Mbps 7-wire interface that is restricted to a 10-Mbps data
rate uses seven of the MII pins for connection to an external Ethernet transceiver.
4.9.8.1
FEC AC Timing
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.9.8.2
MII Receive Signal Timing
The MII receive timing signals consist of FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_RX_CLK frequency. Table 48 lists MII receive channel timings.
1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode.
Figure 39 shows the MII receive signal timings listed in Table 48.
Figure 39. MII Receive Signal Timing Diagram
Table 48. MII Receive Signal Timing
Num.
Characteristic1
Min.
Max.
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M3
M4
M1
M2
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