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参数资料
型号： MCIMX514AJM6C
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封装： 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件页数： 161/172页
文件大小： 2218K
代理商： MCIMX514AJM6C
Electrical Characteristics
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
Freescale Semiconductor
89
Table 80 shows timing characteristics of signals presented in Figure 53 and Figure 54.
Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level)
ID
Parameter
Symbol
Value
Description
Unit
IP5
Display interface clock period
Tdicp
(1)
Display interface clock. IPP_DISP_CLK
ns
IP6
Display pixel clock period
Tdpcp
DISP_CLK_PER_PIXEL
× Tdicp
Time of translation of one pixel to display,
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXEL is received
by DC/DI one access division to n
components.
ns
IP7
Screen width time
Tsw
(SCREEN_WIDTH)
× Tdicp
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter2.
ns
IP8
HSYNC width time
Thsw
(HSYNC_WIDTH)
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
ns
IP9
Horizontal blank interval 1
Thbi1
BGXP
× Tdicp
BGXP—Width of a horizontal blanking
before a first active data in a line. (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
ns
IP10
Horizontal blank interval 2
Thbi2
(SCREEN_WIDTH -
BGXP - FW)
× Tdicp
Width a horizontal blanking after a last
active data in a line. (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
ns
IP12
Screen height
Tsh
(SCREEN_HEIGHT)
× Tsw
SCREEN_HEIGHT— screen height in lines
with blanking
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
ns
IP13
VSYNC width
Tvsw
VSYNC_WIDTH
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
ns
IP14
Vertical blank interval 1
Tvbi1
BGYP
× Tsw
BGYP—width of first Vertical
blanking interval in line.The BGYP should
be built by suitable DI’s counter.
ns
IP15
Vertical blank interval 2
Tvbi2
(SCREEN_HEIGHT -
BGYP - FH)
× Tsw
width of second Vertical
blanking interval in line.The FH should be
built by suitable DI’s counter.
ns
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相关代理商/技术参数
参数描述
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MCIMX515DJM8C 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
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