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参数资料
型号： MCIMX514AJM6C
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封装： 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件页数： 45/172页
文件大小： 2218K
代理商： MCIMX514AJM6C
Electrical Characteristics
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
Freescale Semiconductor
139
4.7.17
USBOH3 Parameters
This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip
USB PHY parameters see Section 4.7.19, “USB PHY Parameters.”
4.7.17.1
USB Serial Interface
In order to support four serial different interfaces, the USB serial transceiver can be configured to operate
in one of four modes:
DAT_SE0 bidirectional, 3-wire mode
DAT_SE0 unidirectional, 6-wire mode
VP_VM bidirectional, 4-wire mode
VP_VM unidirectional, 6-wire mode
The USB controller does not support ULPI Serial mode. Only the legacy serial mode is supported.
Table 111 shows the serial mode signal map for 6-pin Full speed/Low speed (FsLs) serial mode.
Table 112 shows the serial mode signal map for 3-pin FsLs serial mode.
2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Table 111. Serial Mode Signal Map for 6-pin FsLs Serial Mode
Signal
Maps to
Direction
Description
tx_enable
data(0)
In
Active high transmit enable
tx_dat
data(1)
In
Transmit differential data on D+/D–
tx_se0
data(2)
In
Transmit single-ended zero on D+/D–
int
data(3)
Out
Active high interrupt indication
Must be asserted whenever any unmasked interrupt occurs
rx_dp
data(4)
Out
Single-ended receive data from D+
rx_dm
data(5)
Out
Single-ended receive data from D–
rx_rcv
data(6)
Out
Differential receive data from D+/D–
Reserved
data(7)
Out
Reserved The PHY must drive this signal low
Table 112. Serial Mode Signal Map for 3-pin FsLs Serial Mode
Signal
Maps to
Direction
Description
tx_enable
data(0)
In
Active high transmit enable
dat
data(1)
I/O
Transmit differential data on D+/D– when tx_enable is high
Receive differential data on D+/D– when tx_enable is low
se0
data(2)
I/O
Transmit single-ended zero on D+/D– when tx_enable is high
Receive single-ended zero on D+/D– when tx_enable is low
int
data(3)
Out
Active high interrupt indication
Must be asserted whenever any unmasked interrupt occurs
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