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| 型号： | MCP4726A1T-E/MAY |
| 厂商： | Microchip Technology |
| 文件页数： | 40/86页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT NV EEP I2C 6DFN |
| 标准包装： | 3,000 |
| 设置时间： | 6µs |
| 位数： | 12 |
| 数据接口： | EEPROM，I²C，串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 1.10W |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-VDFN 裸露焊盘 |
| 供应商设备封装： | 6-DFN（2x2） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
| 采样率（每秒）： | * |
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2011-2012 Microchip Technology Inc.
DS22272C-page 45
MCP4706/4716/4726
5.3.1.4
Repeated Start Bit
The Repeated Start bit (see Figure 5-5) indicates the
current
master
device
wishes
to
continue
communicating with the current slave device without
releasing the I2C bus. The Repeated Start condition is
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
+ A bit) and not a Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 5-5:
Repeat Start Condition
Waveform.
5.3.1.5
Stop Bit
The Stop bit (see Figure 5-6) Indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of all MCP47X6
devices.
FIGURE 5-6:
Stop Condition Receive or
Transmit Mode.
5.3.2
CLOCK STRETCHING
“Clock Stretching” is something that the receiving
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP47X6 will not stretch the clock signal (SCL)
since memory read access occurs fast enough.
5.3.3
ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a Start or Stop condition. This is
done so that noisy transmissions (usually an extra Start
or Stop condition) are aborted before they corrupt the
device.
FIGURE 5-7:
Typical 8-Bit I2C Waveform Format.
FIGURE 5-8:
I2C Data States and Bit Sequence.
Note 1: A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL goes
from low to high.
SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
SDA
SCL
Sr = Repeated Start
1st Bit
SCL
SDA A / A
P
1st Bit
SDA
SCL
S
2nd Bit
3rd Bit
4th Bit
5th Bit
6th Bit
7th Bit
8th Bit
P
A / A
SCL
SDA
Start
Condition
Stop
Condition
Data allowed
to change
Data or
A valid
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