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| 型号： | MCP4726A1T-E/MAY |
| 厂商： | Microchip Technology |
| 文件页数： | 69/86页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT NV EEP I2C 6DFN |
| 标准包装： | 3,000 |
| 设置时间： | 6µs |
| 位数： | 12 |
| 数据接口： | EEPROM，I²C，串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 1.10W |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-VDFN 裸露焊盘 |
| 供应商设备封装： | 6-DFN（2x2） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
| 采样率（每秒）： | * |
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2011-2012 Microchip Technology Inc.
DS22272C-page 71
MCP4706/4716/4726
8.10
Design Considerations
In the design of a system with the MCP4706/4716/4726
devices, the following considerations should be taken
into account:
8.10.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-10 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 F. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 8-10:
Typical Microcontroller
Connections.
8.10.2
LAYOUT CONSIDERATIONS
Several layout considerations may be applicable to
your application. These may include:
8.10.2.1
Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP47X6’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards
utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is
capable
of
providing.
Particularly
harsh
environments may require shielding of critical signals.
Separate digital and analog ground planes are
recommended. In this case, the VSS pin and the ground
pins of the VDD capacitors should be terminated to the
analog ground plane.
8.10.2.2
PCB Area Requirements
In some applications, PCB area is a criteria for device
selection.
shows
the
typical
package
dimensions and area for the different package options.
The table also shows the relative area factor compared
to the smallest area. For space critical applications, the
DFN package would be the suggested package.
VDD
VSS
MCP
47X
6
0.1 F
PIC
Mi
croco
n
trolle
r
0.1 F
SCL
VOUT
VREF
SDA
Note:
Breadboards and wire-wrapped boards
are not recommended.
TABLE 8-2:
PACKAGE FOOTPRINT (1)
Package
Package Footprint
Pins
Type
Code
Dimensions
(mm)
Ar
e
a
(m
m
2
)
Re
la
tiv
e
Are
a
Length Width
6
SOT-23
CH
2.90
2.70
7.83
1.96
6
DFN
MAY
2.00
4.00
1
Note 1: Does not include recommended land
pattern
dimensions.
Dimensions
are
typical values.
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