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| 型号： | MCP4726A1T-E/MAY |
| 厂商： | Microchip Technology |
| 文件页数： | 55/86页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT NV EEP I2C 6DFN |
| 标准包装： | 3,000 |
| 设置时间： | 6µs |
| 位数： | 12 |
| 数据接口： | EEPROM，I²C，串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 1.10W |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-VDFN 裸露焊盘 |
| 供应商设备封装： | 6-DFN（2x2） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
| 采样率（每秒）： | * |
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2011-2012 Microchip Technology Inc.
DS22272C-page 59
MCP4706/4716/4726
7.0
TERMINOLOGY
7.1
Resolution
The resolution is the number of DAC output states that
divide the full-scale range. For the 12-bit DAC, the
resolution is 212, meaning the DAC code ranges from 0
to 4095.
7.2
Least Significant bit (LSb)
Normally this is thought of as the ideal voltage
difference between two successive codes. This bit has
the smallest value or weight of all bits in the register.
For a given output voltage range, which is typically the
voltage between the Full-Scale voltage and the Zero-
Scale voltage (VOUT(FS) - VOUT(ZS)), it is divided by the
resolution of the device (Equation 7-1).
EQUATION 7-1:
LSb VOLTAGE
CALCULATION
7.3
Monotonicity
Normally this is thought of as the VOUT voltage never
decreasing, as the DAC register code is continuously
incremented by 1 code step (LSb).
7.4
Full-Scale Error (FSE)
The Full-Scale error (see Figure 7-4) is the sum of
Offset error plus Gain error. It is the difference between
the ideal and measured DAC output voltage with all bits
set to one (DAC input code = FFFh for 12-bit DAC).
EQUATION 7-2:
FULL-SCALE ERROR
7.5
Zero-Scale Error (ZSE)
The Zero-Scale error (see Figure 7-4) is the difference
between the ideal and measured VOUT voltage with the
volatile DAC register equal to 000h. The Zero-Scale
error is the same as the Offset error for this case
(volatile DAC register = 000h).
EQUATION 7-3:
ZERO-SCALE ERROR
7.6
Offset Error
The Offset error (see Figure 7-1) is the deviation from
zero voltage output when the volatile DAC register
value = 000h (zero scale voltage). This error affects all
codes by the same amount. The Offset error can be
calibrated by software in application circuits.
FIGURE 7-1:
Offset Error Example.
VLSb =
VOUT(FS) - VOUT(ZS)
2N - 1
2N = 4096 (MCP4726)
1024 (MCP4716)
256 (MCP4706)
FSE =
VOUT(@FS) - VIDEAL(@FS)
VLSb
Where:
FSE is expressed in LSb
VOUT(@FS) is the VOUT voltage when the DAC
register code is at Full-scale.
VIDEAL(@FS) is the ideal output voltage when the
DAC register code is at Full-scale.
VLSb is the delta voltage of one DAC register code
step (such as code 000h to code 001h).
ZSE =
VOUT(@ZS)
VLSb
Where:
FSE is expressed in LSb
VOUT(@ZS) is the VOUT voltage when the DAC
register code is at Zero-scale.
VLSb is the delta voltage of one DAC register code
step (such as code 000h to code 001h).
Analog
Output
Ideal Transfer Function
Actual Transfer Function
DAC Input Code
0
Offset
Error
(ZSE)
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