
NON-DISCLOSURE
AGREEMENT
REQUIRED
List of Figures
Advance Information
MC68HC(9)08LK60 — Rev. 1.0
20
List of Figures
MOTOROLA
Figure
Title
Page
13-1
SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .217
13-2
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .218
13-3
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .220
13-4
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .223
13-5
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
13-6
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .224
13-7
Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . .226
13-8
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .227
13-9
Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . .229
13-10
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . .230
13-11
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .234
13-12
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
13-13
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .241
13-14
SPI Status and Control Register (SPSCR). . . . . . . . . . . . .243
13-15
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .246
14-1
Alert Control Register (ALCR) . . . . . . . . . . . . . . . . . . . . . .249
14-2
Alert Data Register (ALDR) . . . . . . . . . . . . . . . . . . . . . . . .250
14-3
Block Diagram of SPL Reduction Circuit . . . . . . . . . . . . . .252
15-1
LCD Driver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .254
15-2
LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . .255
15-3
LCD Address Register (LCDAR) . . . . . . . . . . . . . . . . . . . .256
15-4
LCD Data Register (LCDDR) . . . . . . . . . . . . . . . . . . . . . . .258
15-5
LCD Backplane Waveforms — 3 BP . . . . . . . . . . . . . . . . .259
15-6
LCD Backplane Waveforms — 5 BP . . . . . . . . . . . . . . . . .260
15-7
LCD Backplane Waveforms — 8 BP . . . . . . . . . . . . . . . . .261
15-8
LCD Backplane Waveforms with Anti-Ghosting — 3 BP . .262
15-9
LCD Voltage Converter Connections . . . . . . . . . . . . . . . . .264
16-1
TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
16-2
TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .268
16-3
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .273
16-4
Timer Status and Control Register (TSC) . . . . . . . . . . . . .280
16-5
Timer Counter Register High (TCNTH) . . . . . . . . . . . . . . .283
16-6
Timer Counter Register Low (TCNTL) . . . . . . . . . . . . . . . .283