List of Figures
MC68HC(9)08LK60 — Rev. 1.0
Advance Information
MOTOROLA
List of Figures
21
NON-DISCLOSURE
AGREEMENT
REQUIRED
Figure
Title
Page
16-7
Timer Modulo Register High (TMODH) . . . . . . . . . . . . . . .284
16-8
Timer Modulo Register Low (TMODL) . . . . . . . . . . . . . . . .284
16-9
Timer Channel 0 Status and Control Register (TSC0) . . . .285
16-10
Timer Channel 1 Status and Control Register (TSC1) . . . .285
16-11
Timer Channel 2 Status and Control Register (TSC2) . . . .286
16-12
Timer Channel 3 Status and Control Register (TSC3) . . . .286
16-13
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
16-14
Timer Channel 0 Register High (TCH0H). . . . . . . . . . . . . .290
16-15
Timer Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . .290
16-16
Timer Channel 1 Register High (TCH1H). . . . . . . . . . . . . .291
16-17
Timer Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . .291
16-18
Timer Channel 2 Register High (TCH2H). . . . . . . . . . . . . .291
16-19
Timer Channel 2 Register Low (TCH2L) . . . . . . . . . . . . . .291
16-20
Timer Channel 3 Register High (TCH3H). . . . . . . . . . . . . .292
16-21
Timer Channel 3 Register Low (TCH3L) . . . . . . . . . . . . . .292
17-1
I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . .294
17-2
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .295
17-3
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .296
17-4
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
17-5
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .298
17-6
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .299
17-7
Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
17-8
Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .301
17-9
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . .302
17-10
Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
18-1
Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
18-2
Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
18-3
Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . .309
18-4
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
18-5
Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
19-1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
19-2
Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . .319