Timer Interface Module (TIM)
Functional Description
MC68HC(9)08LK60 — Rev. 1.0
Advance Information
MOTOROLA
Timer Interface Module (TIM)
275
NON-DISCLOSURE
AGREEMENT
REQUIRED
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
16.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The timer channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS0B bit in timer channel 0 status and control register
(TSC0) links channel 0 and channel 1. The timer channel 0 registers
initially control the pulse width on the TCH0 pin. Writing to the timer
channel 1 registers enables the timer channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the timer channel registers (0 or 1)
that control the pulse width are the ones written to last. TSC0 controls
and monitors the buffered PWM function, and timer channel 1 status and
control register (TSC1) is unused. While the MS0B bit is set, the channel
1 pin, TCH1, is available as a general-purpose I/O pin if the timer pad is
shared with the I/O pad.
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the TCH2 pin. The timer channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS2B bit in timer channel 2 status and control register
(TSC2) links channel 2 and channel 3. The timer channel 2 registers
initially control the pulse width on the TCH2 pin. Writing to the timer
channel 3 registers enables the timer channel 3 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the timer channel registers (2 or 3)
that control the pulse width are the ones written to last. TSC2 controls
and monitors the buffered PWM function, and timer channel 3 status and
control register (TSC3) is unused.