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型号： MCZ33903BD5EK
厂商： Freescale Semiconductor
文件页数： 28/106页
文件大小： 0K
描述： IC SBC CAN HS 5.0V 32SOIC
标准包装： 42
应用： 系统基础芯片
接口： CAN，LIN
电源电压： 5.5 V ~ 28 V
封装/外壳： 32-SSOP（0.295"，7.50mm 宽）裸露焊盘
供应商设备封装： 32-SOICW 裸露焊盘
包装： 管件
安装类型： 表面贴装
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
33903/4/5
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
INTERRUPT
INT pulse duration (refer to SPI for selection. Guaranteed by design)
short (25 to 125 °C)
short (-40 °C)
long (25 to 125 °C)
long (-40 °C)
tINT-PULSE
20
90
25
100
35
40
130
140
s
STATE DIGRAM TIMINGS
Delay for SPI Timer A, Timer B or Timer C write command after entering Normal
mode
(No command should occur within tD_NM.
tD_NM delay definition: from CS rising edge of “Go to Normal mode (i.e. 0x5A00)”
command to CS falling edge of “Timer write” command)
tD_NM
60
-
s
Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense period
and active time, Cyclic Interrupt period, LP mode overcurrent (unless otherwise
noted)(33)
tTIMING-ACC
-10
-
10
%
CAN DYNAMIC CHARACTERISTICS
TXD Dominant State Timeout
tDOUT
300
600
1000
s
Bus dominant clamping detection
tDOM
300
600
1000
s
Propagation loop delay TXD to RXD, recessive to dominant (Fast slew rate)
tLRD
60
120
210
ns
Propagation delay TXD to CAN, recessive to dominant
tTRD
-
70
110
ns
Propagation delay CAN to RXD, recessive to dominant
tRRD
-
45
140
ns
Propagation loop delay TXD to RXD, dominant to recessive (Fast slew rate)
tLDR
100
120
200
ns
Propagation delay TXD to CAN, dominant to recessive
tTDR
-
75
150
ns
Propagation delay CAN to RXD, dominant to recessive
tRDR
-
50
140
ns
Loop time TXD to RXD, Medium Slew Rate (Selected by SPI)
Recessive to Dominant
Dominant to Recessive
tLOOP-MSL
-
200
-
ns
Loop time TXD to RXD, Slow Slew Rate (Selected by SPI)
Recessive to Dominant
Dominant to Recessive
tLOOP-SSL
-
300
-
ns
CAN Wake-up filter time, single dominant pulse detection(30) (See Figure 35)
tCAN-WU1-F
0.5
2.0
5.0
s
CAN Wake-up filter time, 3 dominant pulses detection(31)
tCAN-WU3-F
300
-
ns
CAN Wake-up filter time, 3 dominant pulses detection timeout(32) (See
Figure 36)
tCAN-WU3-TO
-
120
s
Notes
30.
No Wake-up for single pulse shorter than tCAN-WU1 min. Wake-up for single pulse longer than tCAN-WU1 max.
31.
Each pulse should be greater than tCAN-WU3-F min. Guaranteed by design, and device characterization.
32.
The 3 pulses should occur within tCAN-WU3-TO. Guaranteed by design, and device characterization.
33.
Guaranteed by design.
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V
VSUP 28 V, -40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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