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| 型号： | MCZ33903BD5EK |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 50/106页 |
| 文件大小： | 0K |
| 描述： | IC SBC CAN HS 5.0V 32SOIC |
| 标准包装： | 42 |
| 应用： | 系统基础芯片 |
| 接口： | CAN，LIN |
| 电源电压： | 5.5 V ~ 28 V |
| 封装/外壳： | 32-SSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 供应商设备封装： | 32-SOICW 裸露焊盘 |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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Analog Integrated Circuit Device Data
48
Freescale Semiconductor
33903/4/5
FUNCTIONAL DEVICE OPERATION
CYCLIC INT OPERATION DURING LP VDD ON MODE
CYCLIC INT OPERATION DURING LP VDD ON MODE
Principle
This function can be used only in LP VDD ON mode (LP
VDD ON).
When Cyclic INT is selected and device is in LP VDD ON
mode, the device will generate a periodic INT pulse.
Upon reception of the INT pulse, the MCU must
acknowledge the INT by sending SPI commands before the
end of the next INT period in order to keep the process going.
When Cyclic INT is selected and operating, the device
remains in LP VDD ON mode, assuming the SPI commands
are issued properly. When no/improper SPI commands are
sent, the device will cease Cyclic INT operation and leave LP
VDD ON mode by issuing a reset. The device will then enter
into Normal Request mode.
VDD current capability and VDD regulator behavior is
similar as in LP VDD ON mode.
Operation
Cyclic INT period selection: register timer B
SPI command in hex 0x56xx [example; 0x560E for 512ms
cyclic Interrupt period (SPI command without parity bit)].
This command must be send while the device is in Normal
mode.
SPI commands to acknowledge INT: (2 commands)
- read the Random code via the watchdog register address
using the following command: MOSI 0x1B00 device report on
MISO second byte the RNDM code (MISO bit 0-7).
- write watchdog refresh command using the random code
inverted: 0x5A RNDb.
These commands can occur at any time within the period.
Initial entry in LP mode with Cyclic INT: after the device is
set in LP VDD ON mode, with cyclic INT enable, no SPI
command is necessary until the first INT pulse occurs. The
acknowledge process must start only after the 1st INT pulse.
Leave LP mode with Cyclic INT:
This is done by a SPI Wake-up command, similar to SPI
Wake-up from LP VDD ON mode: 0x5C10. The device will
enter into Normal Request mode.
Improper SPI command while Cyclic INT operates:
When no/improper SPI commands are sent, while the
device is in LP VDD ON mode with Cyclic INT enable, the
device will cease Cyclic INT operation and leave LP VDD ON
mode by issuing a reset. The device will then enter into
Normal Request mode.
The figure below (Figure 27) describes the complete
Cyclic Interrupt operation.
Figure 27. Cyclic Interrupt Operation
NORMAL MODE
INT
SPI
Timer B
LP VDD
Cyclic INT period
LP VDD ON MODE
ON mode
Read RNDM code
Write RNDM code inv.
1st period
2nd period
NORMAL
MODE
Cyclic INT period
3rd period
SPI Wake-up: 0x5C10
Write Timer B, select Cyclic INT period (ex: 512 ms, 0x560E)
Write Device mode: LP VDD ON with Cyclic INT enable (example: 0x5C90)
Cyclic INT period
Legend for SPI commands
INT
SPI
RST
RESET and
REQUEST
Prepare LP VDD ON
In LP VDD ON with Cyclic INT
Leave LP
Improper or no
with Cyclic INT
VDD ON Mode
LP VDD ON MODE
Leave LP VDD ON and Cyclic INT due to improper operation
REQUEST
acknowledge SPI command
NORMAL
MODE
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相关代理商/技术参数 |
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|---|---|
| MCZ33903BD5EKR2 | 功能描述:CAN 接口集成电路 SBC W/HIGH SPEED CAN 5V RoHS:否 制造商:Texas Instruments 类型:Transceivers 工作电源电压:5 V 电源电流: 工作温度范围:- 40 C to + 85 C 封装 / 箱体:SOIC-8 封装:Tube |
| MCZ33903BD5R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:SBC Gen2 with CAN High Speed and LIN Interface |
| MCZ33903BS3EK | 功能描述:CAN 接口集成电路 Canvas 32 SL (3.3V) RoHS:否 制造商:Texas Instruments 类型:Transceivers 工作电源电压:5 V 电源电流: 工作温度范围:- 40 C to + 85 C 封装 / 箱体:SOIC-8 封装:Tube |
| MCZ33903BS3EKR2 | 功能描述:CAN 接口集成电路 Canvas 32 SL (3.3V) RoHS:否 制造商:Texas Instruments 类型:Transceivers 工作电源电压:5 V 电源电流: 工作温度范围:- 40 C to + 85 C 封装 / 箱体:SOIC-8 封装:Tube |
| MCZ33903BS3R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:SBC Gen2 with CAN High Speed and LIN Interface |
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