参数资料
型号: MCZ33903BD5EK
厂商: Freescale Semiconductor
文件页数: 97/106页
文件大小: 0K
描述: IC SBC CAN HS 5.0V 32SOIC
标准包装: 42
应用: 系统基础芯片
接口: CAN,LIN
电源电压: 5.5 V ~ 28 V
封装/外壳: 32-SSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 32-SOICW 裸露焊盘
包装: 管件
安装类型: 表面贴装
Analog Integrated Circuit Device Data
90
Freescale Semiconductor
33903/4/5
SERIAL PERIPHERAL INTERFACE
FLAGS AND DEVICE STATUS
FIX AND EXTENDED DEVICE STATUS
For every SPI command, the device response on MISO is
fixed status information. This information is either:
Two Bytes
Fix Status + Extended Status: when a device write
command is used (MOSI bits 15-14, bits C1 C0 = 01)
One Byte
Fix Status: when a device read operation is performed
(MOSI bits 15-14, bits C1 C0 = 00 or 11).
Table 41. Status Bits Description
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MISO
INT
WU
RST
CAN-G
LIN-G
I/O-G
SAFE-G VREG-G CAN-BUS CAN-LOC LIN2 LIN1
I/O-1 I/O-0 VREG-1
VREG-0
Bits
Description
INT
Indicates that an INT has occurred and that INT flags are pending to be read.
WU
Indicates that a Wake-up has occurred and that Wake-up flags are pending to be read.
RST
Indicates that a reset has occurred and that the flags that report the reset source are pending to be read.
CAN-G
The INT, WU, or RST source is CAN interface. CAN local or CAN bus source.
LIN-G
The INT, WU, or RST source is LIN2 or LIN1 interface
I/O-G
The INT, WU, or RST source is I/O interfaces.
SAFE-G
The INT, WU, or RST source is from a SAFE condition
VREG-G
The INT, WU, or RST source is from a Regulator event, or voltage monitoring event
CAN-LOC
The INT, WU, or RST source is CAN interface. CAN local source.
CAN-BUS
The INT, WU, or RST source is CAN interface. CAN bus source.
LIN2
The INT, WU, or RST source is LIN2 interface
LIN/LIN1
The INT, WU, or RST source is LIN1 interface
I/O-0
The INT, WU, or RST source is I/O interface, flag from I/O sub adress Low (bit 7 = 0)
I/O-1
The INT, WU, or RST source is I/O interface, flag from I/O sub adress High (bit 7 = 1)
VREG-1
The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 = 1)
VREG-0
The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 = 0)
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