参数资料
型号: MCZ33903BD5EK
厂商: Freescale Semiconductor
文件页数: 83/106页
文件大小: 0K
描述: IC SBC CAN HS 5.0V 32SOIC
标准包装: 42
应用: 系统基础芯片
接口: CAN,LIN
电源电压: 5.5 V ~ 28 V
封装/外壳: 32-SSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 32-SOICW 裸露焊盘
包装: 管件
安装类型: 表面贴装
Analog Integrated Circuit Device Data
78
Freescale Semiconductor
33903/4/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
REGULATOR, CAN, I/O, INT AND LIN REGISTERS
Table 33. Regulator Register
MOSI First Byte [15-8]
[b_15 b_14] 01_111 [P/N]
MOSI Second Byte, bits 7-0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
01 01_ 111 P
VAUX[1]
VAUX[0]
-
5V-can[1]
5V-can[0]
VDD bal en
VDD bal auto
VDD OFF en
Default state
0
N/A
0
N/A
Condition for default
POR
Bits
Description
b7 b6
VAUX[1], VAUX[0] - Vauxilary regulator control
00
Regulator OFF
01
Regulator ON. undervoltage (UV) and Overcurrent (OC) monitoring flags not reported. VAUX is disabled when UV or OC
detected after 1.0 ms blanking time.
10
Regulator ON. undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after
1.0 ms blanking time.
11
Regulator ON. undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after
25
s blanking time.
b4 b3
5 V-can[1], 5 V-can[0] - 5V-CAN regulator control
00
Regulator OFF
01
Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags not reported. 1.0 ms
blanking time for UV and OC detection. Note: by default when in Debug mode
10
Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags active. 1.0 ms blanking time
for UV and OC detection.
11
Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags active after 25
s blanking
time.
b2
VDD bal en - Control bit to Enable the VDD external ballast transistor
0
External VDD ballast disable
1
External VDD ballast Enable
b1
VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typically 60 mA
0
Disable the automatic activation of the external ballast
1
Enable the automatic activation of the external ballast, if VDD > typically 60 mA
b0
VDD OFF en - Control bit to allow transition into LP VDD OFF mode (to prevent VDD turn OFF)
0
Disable Usage of LP VDD OFF mode
1
Enable Usage of LP VDD OFF mode
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